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| nuvoton 8051 - based microcontroller n79e8 45 n79e84 4 n79e8 4 32 data s heet version: a 2. 6
N79E845/844/8432 data s heet april 23 201 4 page 2 of 183 revision a2. 6 table of c ontents 1 general description ................................................................................................................................... 5 2 features ............................................................................................................................................................ 6 3 parts information li st .............................................................................................................................. 8 4 block diagram ............................................................................................................................................... 9 5 pin configuration ...................................................................................................................................... 10 6 memory organization ............................................................................................................................. 13 6.1 aprom flash memory ........................................................................................................................... 14 6.2 ldrom flash memory .......................................................................................................................... 14 6.3 co nfig - bits ........................................................................................................................................... 14 6.4 on - chip non - volatile data flash ............................................................................................................ 14 6.5 on - chip xram ....................................................................................................................................... 16 6.6 on - chip scratch - pad ram and sfr ....................................................................................................... 16 6.7 working registers ................................................................................................................................... 17 6.8 bit - addressable locations ....................................................................................................................... 18 6.9 stack ........................................................................................................................................................ 18 7 special function register (sfr) .......................................................................................................... 19 8 general 80c51 system control ............................................................................................................ 24 9 i/o port structure a nd operation .................................................................................................... 28 9.1 quasi - bidirectional output configuration .............................................................................................. 28 9.1.1 read - modify - write .................................................................................................................... 29 9.2 open drain output configuration ........................................................................................................... 30 9.3 push - pull output configuration .............................................................................................................. 30 9.4 input only configuration ........................................................................................................................ 31 10 timers/counters ......................................................................................................................................... 34 10.1 timers/counters 0 and 1 ......................................................................................................................... 34 10.1.1 mode 0 (13 - bit timer) .............................................................................................................. 38 10.1.2 mode 1 (16 - bit timer) .............................................................................................................. 39 10.1.3 mode 2 (8 - bit auto - reload timer) .......................................................................................... 39 10.1.4 mode 3 (two separate 8 - bit timers) ....................................................................................... 40 10.2 timer/counter 2 ...................................................................................................................................... 41 10.2.1 i nput capture mode .................................................................................................................. 44 10.2.2 auto - reload mode .................................................................................................................... 48 10.2.3 compare mode ......................................................................................................................... 48 11 watch dog timer (wdt) ............................................................................................................................. 50 11.1 functional description ............................................................................................................................ 50 11.2 applications of watchdog timer reset .................................................................................................. 53 11.3 applications of watchdog timer interrupt ............................................................................................. 54 12 serial port (uart) ....................................................................................................................................... 56 12.1 mode 0 .................................................................................................................................................... 58 12.2 mode 1 .................................................................................................................................................... 60 12.3 mode 2 .................................................................................................................................................... 62 12.4 mode 3 .................................................................................................................................................... 64 12.5 baud rates .............................................................................................................................................. 66 12.6 framing error detection ......................................................................................................................... 67 12.7 multiprocessor communication .............................................................................................................. 67 12.8 automatic address recognition ............................................................................................................. 68 13 serial peripheral in terface (spi) ....................................................................................................... 71 13.1 features ................................................................................................................................................... 71 N79E845/844/8432 data s heet april 23 201 4 page 3 of 183 revision a2. 6 13.2 functiona l description ............................................................................................................................ 71 13.3 spi control registers .............................................................................................................................. 73 13.4 operating modes ..................................................................................................................................... 76 13.4.1 m aster mode ............................................................................................................................. 76 13.4.2 slave mode ............................................................................................................................... 77 13.5 clock formats and data transfer ........................................................................................................... 77 13.6 slave select pin configuration ................................................................................................................ 80 13.7 mode fault detection .............................................................................................................................. 80 13.8 write collision error ............................................................................................................................... 81 13.9 overrun error .......................................................................................................................................... 81 13.10 spi interrupts .......................................................................................................................................... 82 14 keyboard interrupt ( kbi) ....................................................................................................................... 84 15 analog - to - digital converter (a dc) ................................................................................................ 88 16 inter - integrated circuit ( i 2 c) .............................................................................................................. 94 16.1 features ................................................................................................................................................... 94 16.2 functional description ............................................................................................................................ 94 16.2.1 start and stop conditions .................................................................................................. 95 16.2.2 7 - bit address with data format ............................................................................................... 96 16.2.3 acknowledge ............................................................................................................................ 97 16.2.4 arb itration ................................................................................................................................ 98 16.3 control registers of i 2 c .......................................................................................................................... 99 16.4 operation modes ................................................................................................................................... 102 16.4.1 master transmitter mode ....................................................................................................... 102 16.4.2 master receiver mode ............................................................................................................ 103 16.4.3 slave receiver mode .............................................................................................................. 104 16.4.4 slave transmitter mode ......................................................................................................... 105 16.4.5 general call ............................................................................................................................ 106 16.4.6 miscellaneous states ............................................................................................................... 107 16.5 typical structure of i 2 c interrupt service routine ............................................................................... 108 16.6 i 2 c time - out .......................................................................................................................................... 111 16.7 i 2 c interrupts ......................................................................................................................................... 112 17 pulse width modulate d (pwm) .......................................................................................................... 113 17.1 features ................................................................................................................................................. 113 17.2 functional description .......................................................................................................................... 113 18 timed access protect ion(ta) .............................................................................................................. 123 19 interrupt system ...................................................................................................................................... 125 19.1 interrupt sources ................................................................................................................................... 125 19.2 priority level structure ......................................................................................................................... 127 19.3 interrupt response time ....................................................................................................................... 131 19.4 sfr of interrupt .................................................................................................................................... 131 20 in system programmin g (isp) ............................................................................................................... 137 20.1 isp procedure ........................................................................................................................................ 137 20.2 isp command table ............................................................................................................................. 141 20.3 access table of isp programming ....................................................................................................... 142 20.4 isp user guide ...................................................................................................................................... 142 20.5 isp demo code ..................................................................................................................................... 143 21 power management ................................................................................................................................. 146 21.1 idle mode .............................................................................................................................................. 146 21.2 power - down mode ................................................................................................................................ 147 22 clock system .............................................................................................................................................. 149 N79E845/844/8432 data s heet april 23 201 4 page 4 of 183 revision a2. 6 22.1 on - chip rc oscillator .......................................................................................................................... 151 22.2 crystal/resonator .................................................................................................................................. 151 23 power monitoring .................................................................................................................................... 152 23.1 power - on detection ............................................................................................................................... 152 23.2 brown - out detection ............................................................................................................................. 152 24 reset conditions ....................................................................................................................................... 155 24.1 power - on reset ..................................................................................................................................... 155 24.2 bod reset ............................................................................................................................................ 156 24.3 rst pin reset ....................................................................................................................................... 157 24.4 wat chdog timer reset .......................................................................................................................... 157 24.5 software reset ...................................................................................................................................... 158 24.6 boot selection ....................................................................................................................................... 159 24.7 res et state ............................................................................................................................................. 160 25 config bits (config) ................................................................................................................................. 162 25.1 config0 .............................................................................................................................................. 162 25.2 config1 ( N79E845 only) .................................................................................................................. 163 25.3 config2 .............................................................................................................................................. 164 25.4 config3 .............................................................................................................................................. 165 26 instruction sets ....................................................................................................................................... 167 27 in - circuit program (icp ) ........................................................................................................................ 171 28 electrical character istics ............................................................................................................... 173 28.1 absolute maximum ratings .................................................................................................................. 173 28.2 dc electrical characteristics ................................................................................................................ 173 28.3 ac electrical characteristics ................................................................................................................ 177 28.3.1 10- bits sar - adc specification ............................................................................................. 177 28.3.2 4 ~ 24 mhz xtal specifications .......................................................................................... 178 28.3.3 internal rc oscillator specifications 22.1184 mhz/11.0592 mhz .................................. 178 28.3.4 internal rc oscillator specifications 10 khz .................................................................... 179 29 application circuit for emc immunity ......................................................................................... 180 30 package dimensions ................................................................................................................................ 181 30.1 20- pin tssop - 4.4x6.5mm ................................................................................................................. 181 30.2 16- pin sop - 150 mil ............................................................................................................................ 182 31 document revision hi story ................................................................................................................ 183 N79E845/844/8432 data s heet april 23 201 4 page 5 of 183 revision a2. 6 1 general d escription the N79E845/844/8432 8 - bit turbo 51 (4t mode) microcontroller is embedded with 16k [1] /8k/4k bytes flash eprom which can be programmed through universal hardware writer, serial icp (in circuit program) programmer, software isp function. the instruction sets of the N79E845/844/8432 is fully compatible with the standard 8052. the N79E845/844/8432 contain s 16k /8 k /4 k bytes application flash eprom (aprom) memory, 4 kbytes data flash memory , and 2 kbytes load flash eprom (ldrom) memory; 256 bytes direct and indirect ram, 256 bytes xram; 17 i/o with bit - addressable i/o ports; two 16 - bit timers/counters; 7 - channel multiplexed 10 - bit a/d converter; 4 - channel 10- bit pwm; three serial ports includ ing a spi, i 2 c and an enhanced full duplex serial port; 2 - level bod voltage dete c- tion/reset, and power - on reset (por). the N79E845/844/8432 also support s internal rc oscillator at the nominal freque n- cy of 22.1184 mhz. the accuracy of rc oscill ator (22.1184 mhz) is trimmed as 1% under the condition of room te m- perature and v dd = 5v before shipping from by factory trimming mechanism , which peripherals are supported by 14 sources of four - level interrupt capability. to facilitate programming and ve rification, the flash eprom inside the N79E845/844/8432 allow s the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the N79E845/844/8432 microcontroller , featur ing wide operati ng voltage range, built - in rich analog and digital perip h- erals and non - volatile flash memory , is widely suit able for general control and home appliance s . [1] for n79e8 4 5 , data flash and aprom share 16 kbyte s space . N79E845/844/8432 data s heet april 23 201 4 page 6 of 183 revision a2. 6 2 features ? core ? fully static design 8 - bit turbo 51 (4t) cmos microcontroller ? instruction sets fully compatible with the mcs - 51 ? o perating voltage range ? v dd = 4.5v to 5.5v at f osc up to 24mhz ? v dd = 3.0v to 5.5v at internal rc 22.1184mhz ? v dd = 2. 4 v to 5.5v at f osc = 4~ 12 mhz or internal rc 11.0592mhz ? operating temperature range ? - 40 q c ~85 q c ? clock source ? high - speed external oscillator: - up to 24 mhz crystal and resonator (enabled by config - bits ) ? internal rc oscillator: 22.1184mhz/11.0592mhz (selectable by config - bits ) - r 1% at v dd = 5v and 25 q c - r 3% at v dd = 2.7v ~ 5.5v and 25 q c - r 5% at v dd = 2.7v ~ 5.5v and - 10 q c~+70 q c - r 8% at v dd = 2.7v ~ 5.5v and - 40 q c ~ 85 q c ? flexible cpu clock source configurable by config - bits and software ? 8 - bit programmable cpu clock divider(divm) ? on - chip memory ? 1 00,000 erase/write cycles ? n79e8 4 5 : 16 kbyte s shared by aprom and data flash depend ing on config - bits definition s ? n79e8 4 4: 8 kbyte s aprom, 4 kbyte s data flash ? n79e 8 4 3 2 : 4 kbyte s aprom, 4 kbyte s data flash ? aprom, ldrom and data flash security protection ? flash page size as 128 bytes ? 256 bytes of on - chip direct/indirect ram ? 256 bytes of xram , accessed by movx instruction ? on - chip flash programmed through - parallel h/w w riter mode - serial in - circuit - program mode (icp) - software i mplemented isp (in - system - program) ? i/o ports ? maximum 17 i/o pins ? all i/o pin besides p1.2 and p1.3 support 4 software configurable output modes ? software selectable ttl or schmitt trigger input type per port ? 14 interrupt source s with four levels of priority ? led drive capability 38 ma on p10, p11, p14, p16, p17 ? led drive capability 20ma on po rt 0 and port 3 ? timer/counter ? two set s 16- bit t imers/ c ounters N79E845/844/8432 data s heet april 23 201 4 page 7 of 183 revision a2. 6 ? one 16- bit timer with two channel of input captures ? watchdog timer ? programmable watchdog timer ? c lock source supported by internal 10 khz r 50% accuracy rc oscillator ? s erial ports (uart, spi, i 2 c) ? one set of enhanced full duplex uart port with framing error detection and automatic address recognition. ? one set spi with master/slave capability. ? one set i 2 c with master/slave capability ? pwm ? 4 channels 10 - bit pwm outputs with one brake/fault input ? kbi ? 8 - keypad interrupt inputs(kbi) with 8 falling/ rising/ both - edge detection pins selected by software ? a dc ? 10- bit a/d converter ? up to 150 ksps.(sample per second) ? 7 analog input channels ? brown - out de te ctor ? 2 - level ( 3.8 v /2. 7 v) bod detector ? supports interrupt and reset op tions ? por ( power on reset ) ? threshold voltage levels as 2.0v ? built - in power management. ? idle mode ? power - down mode with optional ly enabled wdt functions ? development tools ? hardware writer ? icp programmer ? isp update aprom by uart port N79E845/844/8432 data s heet april 23 201 4 page 8 of 183 revision a2. 6 3 p arts i nformation l ist table 3 - 1 lead free (rohs) parts i nformation l ist part no. aprom ldrom ram data flash package n79e8 4 5a w g 16kb 2 kb 512b share aprom ts sop - 2 0 pin n79e8 4 4a w g 8kb 2 kb 512b 4 kb ts sop - 2 0 pin n79e8432asg 4kb 2kb 512b 4kb sop - 16 pin N79E845/844/8432 data s heet april 23 201 4 page 9 of 183 revision a2. 6 4 block diagram alu stack pointer psw t1 register t2 register acc b instruction decoder & sequencer bus & lock controller dptr timer reg. pc dptr1 port 0 latch port 0 incrementor flash eprom power control & power monitor sfr & ram address 256 bytes ram & sfr timer 0 timer 1 interrupt uart port 1 latch port 1 oscillator xtal1 xtal2 watchdog timer reset block rst vdd gnd p0.0 | p0.7 p1.0 | p1.7 i 2 c, spi pwm kbi on-chip rc oscillator adc 256 xram input capture/ timer 2 port 3 latch port 3 p3.0 | p3.1 on-chip rc 10 khz figure 4 ? 1 N79E845/844/8432 function block diagram N79E845/844/8432 data s heet april 23 201 4 page 10 of 183 revision a2. 6 5 pin configuration 20 pin spiclk, kb0, pwm3, p0.0 icpclk, mosi, pwm2, p1.7 icpdata, miso, pwm1, p1.6 v ss xtal1, p3.1 xtal2, clkout, p3.0 ss, stadc, int1, p1.4 sda, int0, p1.3 ic0, scl, t0, p1.2 p0.1, adc0, pwm0, kb1 p0.2, adc1, brake, kb2 p0.3, adc2, kb3 p0.4, adc3, kb4 p0.5, adc4, kb5 v dd p0.6, adc5, kb6 p0.7, adc6 t1, kb7, ic1 p1.0, txd p1.1, rxd 20 19 18 17 16 15 14 13 1 2 3 5 6 7 8 12 11 9 10 4 rst f igure 5 ? 2 tssop/sop 20- p in assignment 16 pin kb0, pwm3, p0.0 icpclk, pwm2, p1.7 icpdata, pwm1, p1.6 v ss xtal1, p3.1 xtal2, clkout, p3.0 sda, int0, p1.3 p1.2, ic0, scl, t0 p0.1, adc0, pwm0, kb1 p0.2, adc1, brake, kb2 p0.3, adc2, kb3 p0.4, adc3, kb4 v dd p1.0, txd p1.1, rxd 16 15 14 13 12 11 10 9 1 2 3 5 6 7 8 4 rst figure 5 ? 3 sop 16 - p in assignment N79E845/844/8432 data s heet april 23 201 4 page 11 of 183 revision a2. 6 table 5 ? 1 pin description pin number sy m- alternate function type description sop16 sop20 tssop20 1 2 3 12 15 v dd p power supply: supply voltage v dd for operation. 5 5 v ss p ground: ground potential 4 4 /rst i (st) reset: chip reset pin that is l ow active. because reset pin has internal pull - up resistor (about 200 k at v dd = 5v), this pin ca n- not be floating. reset pin should be connected to 1 00 pull - up resistor and 1 0 uf pull - low capacitor. 1 1 p0.0 pwm3 kb0 spiclk i/o port0: port 0 has 4 - type i/o port. its multifunction pins are for pwm0, pwm3, t1, brake, spiclk, adc0~adc6 and kb0~kb7. adc0 ~adc6: adc channel input. kb0 ~ kb7: key board input the pwm0 and pwm3 is pwm output channel. t1: timer 1 external input spiclk: spi - 1 cl ock pin 16 20 p0.1 pwm0 adc0 kb1 i/o 15 19 p0.2 brake adc1 kb2 i/o 14 18 p0.3 adc2 kb3 i/o 13 17 p0.4 adc3 kb4 i/o - 16 p0.5 adc4 kb5 i/o - 14 p0.6 adc5 kb6 i/o - 13 p0.7 t1 adc6 kb7 ic1 i/o 11 12 p1.0 txd i/o port1: port 1 has 4 - type i/o port. its multifunction pins are for txd, rxd, t0, /int0, /int1, scl, sda, stadc, icpdat, icpclk and /ss, miso, mosi. the txd and rxd are uart port the scl and sda are i 2 c function with open - drain port. the icpdat and icpclk are icp (in circuit programming) function pin. the /ss, miso, mosi are spi - 1 function pins. the pwm1 and pwm2 are pwm output channel t0: timer 0 external input ic0/1: input capture pin 10 11 p1.1 rxd i/o 9 10 p1.2 t0 scl ic0 d 8 9 p1.3 /int0 sda d N79E845/844/8432 data s heet april 23 201 4 page 12 of 183 revision a2. 6 table 5 ? 1 pin description pin number sy m- alternate function type description sop16 sop20 tssop20 1 2 3 - 8 p1.4 /int1 stadc /ss i/o stadc: adc trigger by external pin 3 3 p1.6 pwm1 icpdat miso i/o 2 2 p1.7 pwm2 icpclk mosi i/o 7 7 p3 .0 xtal2 clkout i/o port3: port 3 has 4 - type i/o port. its multifunction pins are for xtal1, xtal2 and clkout, clkout: internal rc osc/4 output pin. xtal2: this is the output pin from the internal inverting amplifier. it emits the inverted signal of xtal2. xtal1: this is the output pin from the internal inverting amplifier. it emits the inverted signal of xtal1. 6 6 p3.1 xtal1 i/o [1] i/o type description i: input, o: output, i/o: quasi bi - direction, d: open - drain, p: power pins, st: schmitt trigger. N79E845/844/8432 data s heet april 23 201 4 page 13 of 183 revision a2. 6 6 memory organization the N79E845/844/8432 ha s embedded fl ash eprom includ ing 16k/8k/4k b ytes application program flash m emory ( aprom ), fixed 4k bytes data flash (except the device with 16k aprom ), fixed 2k bytes load rom flash memory ( ldrom ) and config - bits . the N79E845/844/8432 also provide s 256 bytes of on - chip direct/indirect ram and 256 bytes of xram acce ssed by movx instruction. for the device of 16k - byte s aprom , the aprom block and data flash block comprise the 16k bytes embedded flash. the block size is config - bits /software configurable. the N79E845/844/8432 is built with a cmos page - erase. the page - erase operation erases all bytes within a page of 128 bytes. 0000h 16k/8k/4k bytes aprom 07ffh chbda or shbda 0000h data flash data flash memory area page 0 = 128b page 1 = 128b page n =128b data flash 128 bytes/page program memory space flash type config-bits 00ffh 0000h indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh direct/indirect ram accessed by mov instruction 256 bytes on-chip xram xram accessed by movx instruction 000h 0ffh data memory space sram type 16k 16k: N79E845 8k: n79e844 4k: n79e8432 ldrom 3fffh figure 6 -1 N79E845/844/8432 memory map N79E845/844/8432 data s heet april 23 201 4 page 14 of 183 revision a2. 6 6.1 a prom flash memory the N79E845/844/8432 has 16k/8k/4k program memory. all instructions are fetched for execution from this memory area. the movc instruction can also read this memory region. the user application program is located in aprom . when cpu boots from aprom (chpcon.bs=0), cpu starts ex e- cuting the pro gram from address 0000h. if the value of program counter (pc) is over the space of aprom , cpu will execute nop operand and program counter increases one by one until pc reaches 3 fffh then it wraparounds to address 0000h of aprom , the cpu executes the appli cation program again. 6.2 l d rom flash m emory each device of t he N79E845/844/8432 is equipped with 2 kbyte s ldrom stored the isp application program. user may develop the isp function in ldrom for updating application program or data flash. similarly, aprom ca n also re - program ldrom and data flash. the start address of ldrom is at 0 000h corresponding to the physical address of the flash memory. however, when cpu runs in ldrom , cpu automatically re - vectors the ldrom start address to 0000h, therefore user program regards the ldrom as an independent program memory, meanwhile, with all interrupt vectors that cpu provides. 6.3 config - bits there are several bytes of config - bits located config - bits block. the config - bits defin e the cpu initial setting after power up or reset. only hardware parallel writer or hardware icp writer can erase/program config - bits. isp pr o- gram in ldrom can also erase/program config - bits. 6.4 on - chip non - volatile data flash the N79E845/844/8432 additionally has non - volatile data flash , which is non - volatile so that it remains its content even after the power is off. therefore, in general application the user can write or read data which rules as parameters or co n- stants. by the software path, sp mode can erase , written, or read the data flash only . of course, hardware with parallel programmer/writer or icp programmer can also access the data flash. the data flash size is software adjustable i n N79E845 (16kb) by updating the content of shbda. shb da[7:0] repr e- sents the high byte of 16 - bit data flash start address and the low byte is hardware set to 00h. the value of shbda is loaded from the content of config1 (chbda) after all resets. the application program can dynamically adjust the data flash si ze by resetting shbda value. once the data flash size is changed the aprom size is changed accordingly. shbda has time access protect ion while a write to shbda is required. the data flash size will be 15.75k bytes and there will is 256 bytes aprom. the dat a flash size is fixed as 4 kbytes from address 3000h through 3fffh i n n79e8 4 4 /8 4 32. s hbda affects nothing. N79E845/844/8432 data s heet april 23 201 4 page 15 of 183 revision a2. 6 the config bit dfen (config0.0) should be programmed as 0 before access ing the data flash block. if dfen r e- mains its un - programmed value 1, aprom will occupy whole 16 k - byte s block in N79E845 dfen. aprom 0000h 3000h [1] 3fffh [1] the address is [shbda, 00h] while dfen (config0.0) is enabled. 3fffh 0000h data flash 0000h 2000h N79E845 n79e844 chbda or shbda 3000h 0000h 1000h n79e8432 reserved aprom (4kb) data flash (4kb) reserved aprom (8kb) data flash (4kb) figure 6 ? 2 N79E845/844/8432 data flash shbda ? sfr high byte of data flash starting address ( ta protected, N79E845 only ) 7 6 5 4 3 2 1 0 shbda[7:0] [1] r/w address: 9ch reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7:0 shbda[7:0] sfr high byte of data flash starting address this byte is valid only when dfen ( config0 .0) being 0 condition. it is used to dynamic adjust the starting address of the data flash when the application pr o- gram is executing. [1] shbda is loaded from config1 after all resets. N79E845/844/8432 data s heet april 23 201 4 page 16 of 183 revision a2. 6 6.5 on - chip xram the N79E845/844/8432 provide s additional on - chip 256 bytes auxiliary ram called xram to enlarge the ram space. it occupies the address space from 00h through ffh . the 256 bytes of xram are indirectly accessed by move external instruction movx @dptr or movx @ri. (see the demo code belo w.) note that the stack pointer may not be located in any part of xram. figure 6 - 1 shows the memory map for this product series. xram demo code: mov r0,#23h ;write #5ah to xram with address @23h mov a,#5ah movx @r0,a mov r1,#23h ;read from xram with address @23h movx a,@r1 mov dptr,#0023h ;write #5bh to xram with address @0023h mov a,#5bh movx @dptr,a mov dptr,#0023h ;read from xram with address @0023h movx a,@dptr 6.6 on - chip scratch - pad ram and sfr the N79E845/844/8432 provides the on - chip 256 bytes scratch pad ram and special function registers (sfrs) which be accessed by software. the sfrs be accessed only by direct addressing, while the on - chip ram be accessed by either direct or indirect addressing. indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh figure 6 -3 256 bytes ram and sfr since the scratch - pad ram is only 256 byte it can be used only when data contents are small. there are several other sp e- cial purpose ar eas within the scratch - pa d ram , which are described as follows. N79E845/844/8432 data s heet april 23 201 4 page 17 of 183 revision a2. 6 register bank 0 register bank 1 register bank 2 register bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct or indirect accessing ram indirect accessing ram 00h 07h 28h 08h 0fh 10h 17h 18h 1fh 20h 21h 22h 23h 24h 25h 26h 27h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 7fh 80h ffh 00h ffh figure 6 -4 data memory and b it - addressable r egion 6.7 working registers there are four sets of working registers, each consisting of eight 8 - bit registers , which are termed as banks 0, 1, 2, and 3. individual registers within these banks can be directly accessed by separate instructions , which individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at one time the N79E845/844/8432 can work wi th only one pa r- ticular bank. the bank selection is done by setting rs1 - rs0 bits in the psw. the r0 and r1 registers are used to store the address for indirect accessing. N79E845/844/8432 data s heet april 23 201 4 page 18 of 183 revision a2. 6 6.8 bit - addressable locations the scratch - pad ram area from location 20h to 2fh is byte as well as bit - addressable. this means that a bit in this area can be individually addressed. in addition , some of the sfrs are also bit - addressable. the instruction decoder is able to distinguish a bit access from a byte access by the type of the instruc tion itself. in the sfr area, any existing sfr whose ad dress ends in 0 or 8 is bit - addressable. 6.9 stack the scratch - pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the top of the stack. wheneve r a jump, call or interrupt is invoked the return address is placed on the stack. there is no restriction as to where the stack can begin in the ram. by default however, the stack pointer contains 07h at reset. the user can then change this to any value de sired. the sp will point to the last used value. therefore, the sp will be incr e- mented and then address saved onto the stack. conversely, while popping from the stack the contents will be read first, and then the sp is decreased. N79E845/844/8432 data s heet april 23 201 4 page 19 of 183 revision a2. 6 7 special function register (sfr ) the N79E845/844/8432 use s special function registers (sfrs) to control and monitor peripherals and their m odes. the sfrs reside in the register locations 80 ~ ffh and are accessed by direct addressing only. some of the sfrs are bit - addressable . this is very useful in cases where user would like to modify a particular bit directly without changing other bits . t hose which are bit - addressable sfrs end their addresses as 0 h or 8 h . the N79E845/844/8432 contain s all the sfrs present ing in the standard 8051 . however some additional sfrs are built in . therefore, some of unused byte s in the original 8051 have been given new functions. the sfrs are listed as follows . N79E845/844/8432 data s heet april 23 201 4 page 20 of 183 revision a2. 6 table 7 ? 1 N79E845/844/8432 special function registers (sfr) mapping f8 adccon0 - - - - - - eip ff f0 b - - spcr spsr spdr p 0 dids eiph f7 e8 eie kbi e kbif kbls0 kbls1 c2l c2h - ef e0 acc adccon1 adch - c0l c0h c1l c1h e7 d8 wdcon0 * pwmpl pwm0l pwm1l pwmcon0 pwm2l pwm3l pwmcon1 df d0 psw pwmph pwm0h pwm1h - pwm2h pwm3h pwmcon2 d7 c8 t2con t2mod rcomp2l rcom2h tl2 th2 - - cf c0 i2con i2addr - - - - - ta c7 b8 ip saden - - i2dat i2sta i2clk i2toc bf b0 p3 p0m1 p0m2 p1m1 p1m2 iph b7 a8 ie saddr - wdcon1 * - - ispfd ispcn af a0 - - auxr1 pmcr * isptrg * - ispal ispah a7 98 scon sbuf - - shbda * - - chpcon * 9f 90 p1 - capcon0 capcon1 capcon 2 divm p3m1 p3m2 97 88 tcon tmod tl0 tl1 th0 th1 ckcon - 8f 80 p0 sp dpl dph - - - pcon 87 in bold bit - addressable - reserved note: 1. the reserved sfr addresses should be kept in their own initial states. user should never change their values. 2. the sfrs in the column with dark borders are bit - addressable * with ta - protection. (time access protection) N79E845/844/8432 data s heet april 23 201 4 page 21 of 183 revision a2. 6 table 7 ? 2 N79E845/844/8432 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] eip interrupt priority 1 ffh pt2 pspi ppwm pwdi - - pkb pi2 0000 0000b adccon 0 adc control register 0 f8h (f f ) adc.1 ( fe) adc.0 (fd) adcex (fc) adci (fb) adcs (fa) aadr2 (f9) aadr1 (f8) aadr0 0000 00 00b e iph interrupt high priority 1 f7h pt2h pspih ppwmh pwdih - - pkbh pi2h 0000 0000b p0dids port 0 digital input disable f6h p0dids[7:0] 0000 0000b spdr serial peripheral data register f5h spdr[7:0] 0000 0000 b spsr serial peripheral status register f4h spif wcol spiovf modf dismodf - - - 0000 0 000b spcr serial peripheral control register f3h ssoe spien lsbfe mstr cpol cpha spr1 spr0 0000 0100b b b register f0h (f7) b.7 (f6) b.6 (f5) b.5 (f4) b.4 (f3) b.3 (f2) b.2 (f1) b.1 (f0) b.0 0000 0000b c 2h input capture 2 high eeh c2h[7:0] 0000 0000b c2l input capture 2 low edh c2l[7:0] 0000 0000b kbls1 keyboard level select 1 ech kbls1[7:0] 0000 0000b kbls0 keyboard level select 0 ebh kbls0[7:0] 0000 0000b kbif kbi interrupt flag eah kbif[7:0] 0000 0000b kbie keyboard interrupt enable e9h kbie[7:0] 0000 0000b eie interrupt enable 1 e8h (ef) et2 (ee) espi (ed) epwm (ec) ewdi (e7) (e8) ecptf (e9) ekb (e8) ei2 c 0000 0000b c1h input capture 1 high e7h c1h[7:0] 0000 0000b c1l input capture 1 low e6h c1l[7:0] 0000 0000b c0h input capture 0 high e5h c0h[7:0] 0000 0000b c0l input capture 0 low e4h c0l[7:0] 0000 0000b adch adc converter result e2h adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 0000 0000 b adccon1 adc control register1 e1h adcen - - - - - rcclk adc0sel 0000 0000b acc accumulator e0h (e7) acc.7 (e6) acc.6 (e5) acc.5 (e4) acc.4 (e3) acc.3 (e2) acc.2 (e1) acc.1 (e0) acc.0 0000 0000b p wmcon1 pwm control register 1 dfh bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b 0000 0000b pwm3l pwm 3 low bits register deh pwm3.7 pwm3.6 pwm3.5 pwm3.4 pwm3.3 pwm3.2 pwm3.1 pwm3.0 0000 0000b pwm2l pwm 2 low bits register ddh pwm2.7 pwm2.6 pwm2.5 pwm2.4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 0000 0000b pwmcon0 pwm control register 0 dch pwmrun load cf clrpwm pwm3i pwm2i pwm1i pwm0i 0000 0000b pwm1l pwm 1 low bits register dbh pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 0000 0000b pwm0l pwm 0 low bits register dah pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 0000 0000b pwmpl pwm counter low register d9h pwmp0.7 pwmp0.6 pwmp0.5 pwmp0.4 pwmp0.3 pwmp0.2 pwmp0.1 pwmp0.0 0000 0000b wdcon0 [4] [3] watch - dog control 0 d8h (df) wdten (de) wdclr (dd) wdtf (dc) widpd (db) wdtrf (da) wps2 (d9) wps1 (d8) wps0 power - on c000 0000b watch reset c0uu 1uuub other reset c0uu uuuub p wmcon2 pwm control register 2 d7h - - - - fp1 fp0 - bkf 0000 0000b pwm3h pwm 3 high bits register d6h - - - - - - pwm3.9 pwm3.8 0000 0000b pwm2h pwm 2 high bits register d5h - - - - - - pwm2.9 pwm2.8 0000 0000b pwm1h pwm 1 high bits register d3h - - - - - - pwm1.9 pwm1.8 0000 0000b pwm0h pwm 0 high bits register d2h - - - - - - pwm0.9 pwm0.8 0000 00 00b pwmph pwm counter high register d1h - - - - - - pwmp0.9 pwmp0.8 0000 0000b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 0000 0000b th2 timer 2 msb cdh th2[7:0] 0000 0000b N79E845/844/8432 data s heet april 23 201 4 page 22 of 183 revision a2. 6 table 7 ? 2 N79E845/844/8432 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] tl2 timer 2 lsb cch tl2[7:0] 0000 0000b rcomp2h timer 2 reload msb cbh rcomp2h[7:0] 0000 0000b rcomp2l timer 2 reload lsb cah rcompl2[7:0] 0000 0000b t2mod timer 2 mode c9h lden t2div[2:0] capcr compcr ldts[1:0] 0000 0000b t2con timer 2 control c8h (cf) tf2 - - - - (ca) tr2 - (c8) rl2 cp/ 0000 0000b t a timed access protection c7h 1111 1111 b i2addr i2c address c1h addr[7:1] gc 0000 0000b i2con i2c control register c0h (c 7) - (c 6) i2cen (c 5) sta (c 4) sto (c 3) si (c 2) aa (c 1) - (c0 ) - 0000 0000 b i 2toc i2c time - out counter register bfh - - - - - i2tocen div i2tof 0000 0000b i2clk i2c clock rate beh i2clk[7:0] 0000 0000b i2sta i2c status register bdh i2sta [7:3 ] 0 0 0 1111 1000b i2dat i2c data register bch i2dat[7:0] 0000 0000 b saden slave address mask b9h saden[7:0] 0000 0000b ip interrupt priority b8h (bf) pcap (be) padc (bd) pbo d (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 0000 0000b i ph interrupt high priority b7h pcaph padch pbo d h psh pt1h px1h pt0h px0h 0000 0000b p1m2 port 1 output mode 2 b4h p1m2.7 p1m2.6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 0000 0000b p1m1 port 1 output mode 1 b3h p1m1.7 p1m1.6 - p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 0000 0000b p0m2 port 0 output mode 2 b2h p0m2[7:0] 0000 0000b p0m1 port 0 output mode 1 b1h p0m1[7:0] 0000 0000b p3 port3 b0h - - - - - - (b1) x1 (b0) x2 clkout 0000 0011 b i spcn isp control register afh ispa17 ispa16 foen fcen fctrl3 fctrl2 fctrl1 fctrl0 0011 0000b ispfd isp flash data register aeh ispfd[7:0] 0000 0000b wdcon1 [4] watch - dog control1 abh - - - - - - - ewrst 0000 0000b saddr slave address a9h saddr[7:0] 00000000b ie interrupt enable a8h (af) ea (ae) eadc (ad) ebod (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0000 0000b i spah isp flash address high - byte a7h ispah[7:0] 0000 0000b ispal isp flash address low - byte a6h ispal[7:0] 0000 0000b isptrg [4] isp trigger register a4h - - - - - - - ispgo 0000 0000b pmcr [2][4] power monitor control register a3h boden bov - borst bof - - - power - on cc0c 100xb bor reset uu0u 100x b other reset uu 0u 000x b auxr1 aux function register a2h - - - - - - 0 dps 0000 0000b chpcon [4] chip control 9fh swrst ispf (read only) ldue - - - bs [3] ispen power - on 0000 00c0b other reset 0000 00c 0b shbda [4] high - byte data flash start address 9ch shbda[7:0], shbda initial by chbda power on cccc ccccb other reset uuuu uuuub sbuf serial buffer 99h sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 0000 0000b N79E845/844/8432 data s heet april 23 201 4 page 23 of 183 revision a2. 6 table 7 ? 2 N79E845/844/8432 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0000 0000b p3m2 port 3 output mode 2 97h - - - - - enclk p3m2.1 p3m2.0 00000 000b p3m1 port 3 output mode 1 96h p3s - p1s p0s t1oe t0oe p3m1.1 p3m1.0 00000000b divm cpu clock divide register 95h divm[7:0] 0000 0000b capcon2 input capture control 2 94h - - enf1 enf0 - - - - 0000 0000b capcon1 input capture control 1 93h - - cap1ls1[2:0] cap1ls1[2:0] 0000 0000b capcon0 input capture control 0 92h - - capen1 capen0 - - capf1 capf0 0000 0000b p1 port 1 90h (97) p17 (96) p16 - (94) p14 (93) p13 (92) p12 (91) p11 (90) p10 1111 1111b ckcon clock control 8eh - - - t1m t0m - - - 0000 0000 b th1 timer high 1 8dh th1[7:0] 0000 0000b th0 timer high 0 8ch th0[7:0] 0000 0000b tl1 timer low 1 8bh tl1[7:0] 0000 0000b tl0 timer low 0 8ah tl0[7:0] 0000 0000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0000 0000b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl power - on 0001 0000b other reset 000u 0000b dph data pointer high 83h dph[7:0] 0000 0000b dpl data pointer low 82h dpl[7:0] 0000 0000b sp stack pointer 81h sp[7:0] 0000 0111b p0 port 0 80h (87) p07 (86) p06 (85) p05 (84) p04 (83) p03 (82) p02 (81) p01 (80) p00 1111 1111b note : b its marked in " - " should be kept in their own initial states. user should never change their values. note: [1.] ( ) item means the bit address in bit - addressable sfrs. [2.] bod en , bo v and borst are initialized by config2 at power - on reset, and keep unchanged at any other resets. if bod en =1, bof will be automatically set by hardware at power - on reset, and keeps unchanged at any other resets. [3.] initialized by power - on reset. wdten =/c wdten ; bs=/cbs; [4.] with ta - protection. (time access protection) [5.] notation ? c ? means the bit is defined by config - bits ; ? u ? means the bit is unchanged after any reset except power - on reset. [6.] reset value symbol description. 0: logic 0, 1: logic 1, u: unchanged, x: , c: initial by config . N79E845/844/8432 data s heet april 23 201 4 page 24 of 183 revision a2. 6 8 general 80 c 51 system control a or acc ? accumulator (bit - addressable) 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 r/w r/w r/w r/w r/w r/w r/w r/w address: e0h reset value: 0000 0000b bit name description 7:0 acc[7:0] accumulator. the a or acc register is the standard 8051 accumulator for arithmetic operation. b ? b register (bit - addressable) 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 r/w r/w r/w r/w r/w r/w r/w r/w address: f0h reset value: 0000 0000b bit name description 7:0 b[7:0] b r egister the b register is the other accumulator of the standard 8051 . it is used mainly for mul and div operations. sp ? stack pointer 7 6 5 4 3 2 1 0 sp[7:0] r/w address: 81h reset value: 0000 0111b bit name description 7:0 sp[7:0] stack p ointer the stack pointer stores the scratch - pad ram address where the stack begins. it is incr e- mented before data is stored during push or call instructions. note that the default value of sp is 07h. it causes the stack to begin at location 08h. N79E845/844/8432 data s heet april 23 201 4 page 25 of 183 revision a2. 6 dpl ? data pointer low byte 7 6 5 4 3 2 1 0 dpl [7:0] r/w address: 8 2 h reset value: 0000 0000b bit name description 7:0 dpl [7:0] data p ointer l ow b yte this is the low byte of the standard 8051 16 - bit data pointer. dpl com bined with dph serve as 1 6 - bit data pointer dptr to address non- scratch - pad memory or program memory . dph ? data pointer high byte 7 6 5 4 3 2 1 0 dph[7:0] r/w address: 83h reset value: 0000 0000b bit name description 7:0 dph[7:0] data pointer high byte this is the high byte of the standard 8051 16- bit data pointer. dph com bined with dpl serve as 1 6 - bit data pointer dptr to address non- scratch - pad memory or program memory . psw ? program status word (bit - addressable) 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r address: d0 h reset value: 0000 0000b bit name description 7 cy carry f lag for a adding or subtracting operation, cy will be set when the previous operation resulted in a carry - out from or a borrow - in to the most significant bit, otherwise cleared. if the previous operation is mul or div, cy is always 0. cy is affected by da a instruction which indicates that if the original bcd sum is greater than 100. for a cjne branch, cy will be set if the first unsigned integer value is less than the second one. otherwise, cy will be cleared. 6 ac auxiliary c arry set when the previous operation resulted in a carry - out from or a borrow - in to the 4th bit of the low order nibble, otherwise cleared. N79E845/844/8432 data s heet april 23 201 4 page 26 of 183 revision a2. 6 bit name description 5 f0 user f lag 0 the general - purpose flag that can be set or cleared by the user. 4 rs1 register bank s electing b its the two bits select one of four banks in which r0 ~ r7 locate. rs1 rs0 register bank ram address 0 0 0 00 ~ 07 h 0 1 1 08 ~ 0f h 1 0 2 10 ~ 17 h 1 1 3 18 ~ 1f h 3 rs0 2 ov overflow f lag ov is used for a signed character operands. for an add or addc instruction, ov will be set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6. otherwise, ov is cleared. ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative ope r- ands. for a subb, ov is set if a borrow is needed into bit6 but not into bit 7, or into bit7 but not bit 6. otherwise, ov is cleared. ov in dicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number. for a mul, if the product is greater than 255 ( 0 0ffh), ov will be set. otherwise, it is cleared. for a div, it is normally 0. however, if b had originally contained 00h, the values returned in a and b will be undefined. meanwhile, the ov will be set. 1 f1 user f lag 1 the g eneral purpose flag that can be set or cleared by the user via software . 0 p parity f lag set to 1 to indicate an odd number of ones in the accumulator. cleared for an even number of ones. it performs even parity check. table 8 ? 1 instructions that a ffect f lag s ettings instruction cy ov ac instruction cy ov ac add x [1] x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, /bit x div 0 x orl c, bit x da a x orl c, /bit x rrc a x mov c, bit x N79E845/844/8432 data s heet april 23 201 4 page 27 of 183 revision a2. 6 instruction cy ov ac instruction cy ov ac rlc a x cjne x setb c 1 [1] x indicates the modification is depend ent on the result of the instruction pcon ? power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 3 gf1 general p urpose f lag 1 the general purpose flag that can be set or cleared by the user. 2 gf0 general p urpose f lag 0 the general purpose flag that can be set or cleared by the user. general 80c51 support one dptr but the N79E845/844/8432 support two dptrs by switching auxr1.dps. the se t- ting is as follows : auxr1 ? aux function resgister - 1 7 6 5 4 3 2 1 0 - - - - - - 0 dps - - - - - - r r/w address: a2h reset value: 0000 0000b bit name description 0 dps dual data pointer select ion 0 = s elect dptr of standard 8051. 1 = s elect dptr1 N79E845/844/8432 data s heet april 23 201 4 page 28 of 183 revision a2. 6 9 i/o port s tructure and o peration for N79E845/844/8432 , t here are four i/o ports port 0, port 1, port2 and port 3. if us ing on- chip rc oscillator and reset pin configurations, the N79E845/844/8432 can support up to 17 pins. all i/o pins besides p1.2 and p1.3 can be co n- figured to one of four types by software as shown in the following table. table 9 ? 1 setting t able for i/o ports s tructure pxm1.y pxm2.y port i/o mode 0 0 quasi - bidirectional 0 1 push - pull 1 0 input only (high impedance) 1 1 open drain note: p1.2 and p1.3 are no t effect ive in this table. after reset, these pins are in quasi - bidirectional mode except p1.2 and p1.3 pins . the p1.2 and p1.3 are dedicating open - drain pin for i2c interface after reset. each i/o port of t he N79E845/844/8432 may be selected to use ttl level inputs or schmitt inputs by p(n)s bit on p3m 1 register; where n is 0 , 1 or 3 . when p(n)s is set to 1, ports are selected schmitt trigger inputs on port(n). the p 3 .0 (xtal2) can be configured as clock output when used on - chip rc is clock source, and the frequency of clock output is divided by 4 on on - chip rc clock. 9.1 quasi - bidirectional output configuration the default port configuration for standard t he N79E845/844/8432 i/o ports are the ? q uasi - bidirectional ? mode that is common on the 80c51 and most of its derivatives. this type rule s as both input and output. when the port outputs logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a large current. in the quasi bidirectional i/o structure, there are three pull - up transistors. each of them serves different purposes. one of these pull - ups, called the ?very weak? pull - up, is turned on wheneve r the port latch co n- tains logic 1 . the ? very weak ? pull - up sources a very small current that will pull the pin high if it is left floating. a second pull - up, called the ?weak? pull - up, is turned on when the outside port pin itself is at logic 1 level. this pull - up provides the pri mary source current for a quasi - bidirectional pin that is outputting 1 . if a pin that has logic 1 on it is pulled low by an external device, the ? weak ? pull - up turns off, and only the ? very weak ? pull - up remains on. to pull the pin low under these conditions, the external device has to sink enough current (larger than i tl ) to overcome the ? weak ? pull - up and make the voltage on the port pin below its input threshold (lower than v il ) . the third pull - up is the ?strong? pul l - up. this pull - up is used to speed up low - to - high transitions on a quasi - bidirectional port pin when the port latch changes from a logic 0 to logic 1 . when this occurs, the strong pull - up turns on for two - N79E845/844/8432 data s heet april 23 201 4 page 29 of 183 revision a2. 6 peripheral - clock time to pull the port pin high qu ickly. then it turns off and ?weak: pull - up continues remaining the port pin high . the quasi bidirectional port structure is shown below . port pin 2-peripheral- clock delay input port latch p p p n v dd strong very weak weak figure 9 ? 1 quasi bi - direction i/o structure 9.1.1 read - modify - write in the standard 8051 instruction set, user should watch out for one kind of instructions, read - modify - write in structions . instead of the normal instructions, the read - modify - write instructions read the internal port latch (p x in sfrs) rather than the external port pin state. this kind of instructions read the port sfr value, modify it and write back to the port sfr. read - modify - write instructions are listed as follows. in s truction description anl logical and. (anl px,a and anl px,direct) orl logical or. (orl px,a and orl px,direct) xrl logical exclusive or. (xrl px,a and xrl px,direct) jbc jump if bit = 1 and clear it. (jbc px.y,label) cpl complement bit. (cpl px.y) inc increment. (inc px) dec decrement. (dec px) djnz decrement and jump if not zero. (djnz px,label) mov px.y,c move carry bit to px.y. clr px.y clear bit px.y. setb px.y set bit px.y. the last three seems not obvious ly read - modify - write instructions but actually they are. they read the entire port latch value , modify the changed bit, and then write the new value back to the port latch. N79E845/844/8432 data s heet april 23 201 4 page 30 of 183 revision a2. 6 9.2 open drain output configuration the open drain output configuration turns off all pull - ups and only drives the pull - down transistor of the port driver when the port latch contains logic 0. to be used as a logic output, a port configured in this manner should have an external pull - up, typically a resistor tied to v dd . the pull - down for this mode is the same as for the qu asi - bidirectional mode. the open drain port configuration is shown below . port pin port latch data n input data figure 9 -2 open drain output 9.3 push - pull output configuration the push - pull output configuration has the same pull - down structure as both the open drain and the quasi - bidirectional output modes, but provides a continuous strong pull - up when the port latch contains logic 1. the push - pull mode may be used when more sou rce current is needed from a port output. the push - pull port configuration is shown in figure 9 - 2 . the two port pins that cannot be configured are p1.2 (scl) and p1.3 (sda) . the port pins p1.2 and p1.3 are permanently co n- figured as open drain outputs. they may be used as inputs by writing ones to their respective port latches. additionally, port pins p3.0 and p3 .1 are disabled for both input and output if one of the crystal oscillator options is chosen. those o p- tions are described in the oscillator section. when port pins are driven high at reset, they are in quasi - bidirectional mode and therefore do not source large amounts of current. every output on the N79E845/844/8432 may potentially be used as a 38 ma sink led drive output. how ever, there is a maximum total output current for all ports which should not be exceeded. all ports pins of the N79E845/844/8432 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is facto ry set to approximately 10 ns rise and fall times. the bits in the p 3 m1 re g- ister that are not used to control configuration of p 3.1 and p3 .0 are used for other purposes , which bits can enable schmitt trigger inputs on each i/o port, enable toggle outputs f rom timer 0 and timer 1, and enable a clock output if either the internal rc oscillator or external clock input is being used. the last two functions are described in the timers/counters and oscillator sections respectively. each i/o port of the N79E845/84 4/8432 may be selected to use ttl level inputs or schmitt inputs with hysteresis. a single configuration bit determines this selection for the entire port. N79E845/844/8432 data s heet april 23 201 4 page 31 of 183 revision a2. 6 port pin input data port latch data p n vdd figure 9 -3 push - pull output 9.4 input only configuration by setting this mode; the ports are only input mode . after setting this mode, the pin will be hi - impendence . p0 ? port 0 (bit - addressable) 7 6 5 4 3 2 1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p01 p00 r/w r/w r/w r/w r/w r/w r/w r/w address: 80h reset value: 1111 1111b bit name description 7:0 p0[7:0] port 0. port 0 is an 8 - bit quasi bidirectional i/o port. p1 ? port 1 (bit - addressable) 7 6 5 4 3 2 1 0 p17 p16 - p14 p13 p12 p11 p10 r/w r/w - r/w r/w r/w r/w r/w address: 90h reset value: 1111 1111b bit name description 7:0 p1[7:0] port 1 these pins are in quasi - bidirectional mode except p1.2 and p1.3 pins. the p1.2 and p1.3 are dedicating open - drain pin s for i 2 c interface after reset. N79E845/844/8432 data s heet april 23 201 4 page 32 of 183 revision a2. 6 p3 ? port 3 (bit - addressable) 7 6 5 4 3 2 1 0 - - - - - - p31 p30 - - - - - - r/w r/w address: b0h reset value: 0000 0011b bit name description 7:2 - reserved 1 p3.1 x1 or i/o pin by alternative. 0 p3.0 x2 or clkout or i/o pin by alternative. p0m1 ? port 0 o utput mode1 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b1h reset value: 0000 0000b p0m2 ? port 0 o utput mode2 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h reset value: 0000 0000b p1m1 ? port 1 o utput mode1 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 - p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 r/w r/w - r/w r/w r/w r/w r/w address: b3h reset value: 0000 0000b p1m2 ? port 1 o utput mode2 7 6 5 4 3 2 1 0 p1m2.7 p1m2 .6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 r/w r/w - r/w r/w r/w r/w r/w address: b4h reset value: 0000 0000b p3m1 ? port3 output mode1 7 6 5 4 3 2 1 0 p3s - p1s p0s t1oe t0oe p3m1.1 p3m1.0 r/w - r/w r/w r/w r/w r/w r/w address: 96h reset value: 0000 0000b bit name description 7 p3s enable schmitt trigger inputs on port 3. 6 - reserved N79E845/844/8432 data s heet april 23 201 4 page 33 of 183 revision a2. 6 bit name description 5 p1s enable schmitt trigger inputs on port 1. 4 p0s enable schmitt trigger inputs on port 0. 1 p3m1.1 c ontrol the output configuration of p3.1. 0 p3m1.0 c ontrol the output configuration of p3.0. p3m2 ? port3 output mode2 7 6 5 4 3 2 1 0 - - - - - enclk p3m2.1 p3m2.0 - - - - - r/w r/w r/w address: 97h reset value: 0000 0000b bit name description 7:3 - reserved 0 enclk c lock o utput to xtal2 p in (p3.0) enable if the clock is from internal rc, the frequency of p3.0 is internal rc/4 (22.1184mhz/4). 1 p3m2.1 refer to table 9 - 1 setting t able for i/o port s tructure 0 p3m2.0 N79E845/844/8432 data s heet april 23 201 4 page 34 of 183 revision a2. 6 10 timers/counters the N79E845/844/8432 has three 16- bi t programmable timer s /counters. 10.1 timer s /counters 0 and 1 timer/counter 0 and 1 i n t he N79E845/844/8432 is two 16 - bit timer s /c ounters. each of them has two 8 - bit registers that form the 16 bit counting register. for timer/coun ter 0 they are th0, the upp er 8 - bi t register, and tl0, the lower 8 - bit register. similar timer/counter 1 has two 8 - bit registers, th1 and tl1. tcon and tmod can configure modes of ti m- er/counter 0 and 1. they have additional timer 0 or timer 1 overflow toggle output enable feature as compare to conventional timers/counters . this timer overflow toggle output can be configured to automatically toggle t0 or t1 pin output whenever a timer ove r- flow occurs. when con figured as a ?timer?, the timer counts clock cycles. the timer clock can be programmed to be thought of as 1/12 of the clock system or 1/4 of the clock system . in the ?counter? mode, the register is incremented on the falling edge of the external input pin , t0 in case of timer 0, and t1 for timer 1. the t0 and t1 inputs are sampled in every machine - cycle at c4. if the sampled value is high in one machine - cycle and low in the next, then a valid high to low transition on the pin is recognized and the count re gister is incremented. since it takes two machine - cycles to recognize a negative tra n- sition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. in either the ?timer? or ?counter? mode, the count register wi ll be updated at c3. therefore, in the ?timer? mode, the recognized negative transition on pin t0 and t1 can cause the count register value to be updated only in the machine - cycle following the one in which the negative edge was detected. the ?timer? or ?c ounter? function is selected by the ? t c/ ? bit in the tmod special function register. each ti m- er/counter has one selection bit for its own; bit 2 of tmod selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each timer/counter can be set to operate in any one of four possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. the N79E845/844/8432 can operate like the standard 8051/52 family, counting at the rate o f 1/12 of the clock speed, or in turbo mode, counting at the rate of 1/4 clock speed. the speed is controlled by the t0m and t1m bits in ckcon, and the default value is zero, which uses the standard 8051/52 speed. ckcon ? clock control 7 6 5 4 3 2 1 0 - - - t1m t0m - - - - - - r/w r/w - - - N79E845/844/8432 data s heet april 23 201 4 page 35 of 183 revision a2. 6 address: 8eh reset value: 0000 0000b bit name description 7:5 - reserved 4 t1m timer 1 c lock s elect: 0 = timer 1 uses a divide by 12 clocks. 1 = timer 1 uses a divide by 4 clocks. 3 t0m timer 0 c lock s elect: 0 = timer 0 uses a divide by 12 clocks. 1 = timer 0 uses a divide by 4 clocks. 2:0 - reserved tmod ? timer 0 and 1 mode 7 6 5 4 3 2 1 0 gate t c/ m1 m0 gate t c/ m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w address: 89h reset value: 0000 0000b bit name description 7 gate timer 1 g ate c ontrol 0 = timer 1 will clock when tr1 = 1 regardless of 1 int logic level. 1 = timer 1 will clock only when tr1 = 1 and 1 int is logic 1. 6 t c/ timer 1 counter/timer s elect ion 0 = timer 1 is incremented by internal peripheral clocks. 1 = timer 1 is incremented by the falling edge of the external pin t1. 5 m1 timer 1 m ode s elect. m 1 m 0 timer 1 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl1[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th1 1 1 mode 3 : timer 1 halted 4 m0 3 gate timer 0 g ate c ontrol 0 = timer 0 will clock when tr0 = 1 regardless of nt0 i logic level. 1 = timer 0 will clock only when tr 0 = 0 and 0 int is logic 1. 2 t c/ timer 0 counter/timer s elect ion 0 = timer 0 is incremented by internal peripheral clocks. 1 = timer 0 is incremented by the falling edge of the external pin t0. 1 m1 timer 0 mode select N79E845/844/8432 data s heet april 23 201 4 page 36 of 183 revision a2. 6 bit name description 0 m0 m 1 m 0 timer 0 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl0[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th0 1 1 mode 3 : tl0 as a 8 - bit timer/counter and th0 as a 8 - bit timer tcon ? timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w address: 8 8 h reset value: 0000 0000b bit name description 7 tf1 timer 1 o verflow f lag this bit is set when timer 1 overflows. it is automatically cleared by hardware when the program executes the timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 r un c ontrol 0 = timer 1 is halted. clearing this bit will halt timer 1 and the current count will be preserved in th1 and tl1. 1 = timer 1 is enabled. 5 tf0 timer 0 o verflow f lag this bit is set when timer 0 overflows. it is automatically cleared via hardware when the program executes the timer 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 r un c ontrol 0 = timer 0 is halted. clearing this bit will halt timer 0 and the current count will be preserved in th0 and tl0. 1 = timer 0 is enabled. N79E845/844/8432 data s heet april 23 201 4 page 37 of 183 revision a2. 6 tl0 ? timer 0 low byte 7 6 5 4 3 2 1 0 tl0 [7:0] r/w address: 8 a h reset value: 0000 0000b bit name description 7:0 tl0[7:0] timer 0 l ow b yte the tl0 register is the low byte of the 16 - bit timer 0. th0 ? timer 0 high byte 7 6 5 4 3 2 1 0 th0[7:0] r/w address: 8ch reset value: 0000 0000b bit name description 7:0 th0[7:0] timer 0 h igh b yte the th0 register is the high byte of the 16 - bit timer 0. tl1 ? timer 1 low byte 7 6 5 4 3 2 1 0 tl1[7:0] r/w address: 8bh reset value: 0000 0000b bit name description 7:0 tl1[7:0] timer 1 l ow b yte the tl1 register is the low byte of the 16 - bit timer 1. th 1 ? timer 1 high byte 7 6 5 4 3 2 1 0 th1[7:0] r/w address: 8dh reset value: 0000 0000b bit name description 7:0 th1[7:0] timer 1 h igh b yte the th1 register is the high byte of the 16 - bit timer 1. N79E845/844/8432 data s heet april 23 201 4 page 38 of 183 revision a2. 6 p3m1 ? port3 output mode1 7 6 5 4 3 2 1 0 p3s - p1s p0s t1oe t0oe p3m1.1 p3m1.0 r/w - r/w r/w r/w r/w r/w r/w address: 96h reset value: 0000 0000b bit name description 3 t1oe p0.7 pin is toggled whenever timer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 2 t0oe p1.2 pin is toggled whenever timer 0 overflows. the output frequency is therefore one - half of the timer 0 overflow rate. 10.1.1 mode 0 (13 - bit timer) in mode 0, the timers/counters act as a 8 - bit counter with a 5 - bit, divide by 32 pre - scale. in this mode we have 1 3 - bit ti m- er/counter. the 13 - bit counter consists of 8 bits of thx and 5 lower bits of tlx. the upper 3 bits of tlx are ignor ed. the negative edge of the clock is increments count in the tlx register. when the fifth bit in tlx moves from 1 to 0, then the count in the thx register is incremented. when the count in thx moves from ffh to 00h, then the overflow flag tfx in tcon sfr is set. the counted input is enabled only if trx is set and either gate = 0 or intx = 1. when t c/ is set to 0, then it will count clock cycles, and if t c/ is set to 1, then it will count 1 to 0 transitions on t0 (p1.2) for timer 0 and t1 (p0.7) for timer 1. when the 13 - bit count reaches 1fffh , the next count will cause it to rollover to 0000h. the timer overflow flag tfx of the relevant timer is set and if enabled an interrupts will occur. f sys 1 / 12 0 1 0 4 7 0 7 tfx th 0 ( th 1) tl 0 ( tl 1) interrupt t 0/t 1 ( c/t = tmod .6) c/t = tmod .2 gate int 0/int 1 tf 0 ( tf 1 ) tr 0/ tr 1 1 / 4 0 1 t 0m = ckcon .3 ( t 1m = ckcon .4) 0 1 1 t 0oe p 1.2 ( p 0.7) pin p 1.2 ( p 0.7) sfr ( t 1oe ) t 0oe ( t 1oe ) en figure 10? 1 timers/counters 0 and 1 in mode 0 N79E845/844/8432 data s heet april 23 201 4 page 39 of 183 revision a2. 6 10.1.2 mode 1 (16 - bit timer) mode 1 is similar to mode 0 except that the counting register s are fully used a s 1 6 - bit counter. rollover occurs when a count moves ffff h to 0000h . the t imer overflow flag tfx of the relevant timer/counter is set and an interrupt will occur s if enabled . f sys 1 / 12 0 1 0 4 7 0 7 tfx th 0 ( th 1) tl 0 ( tl 1) interrupt t 0/t 1 ( c/t = tmod .6) c/t = tmod .2 gate int 0/int 1 tf 0 ( tf 1 ) tr 0/tr 1 1 / 4 0 1 t 0m = ckcon .3 ( t 1m = ckcon .4) 0 1 1 t 0oe p 1.2 ( p 0.7) pin p 1.2 ( p 0.7) sfr ( t 1oe ) t 0oe ( t 1oe ) en figure 10? 2 timers/counters 0 and 1 in mode 1 10.1.3 mode 2 (8 - bit auto - reload timer) in mode 2, the timer / counter is in a uto - reload mode . in this mode, tlx acts as an 8 - bit count register whereas thx holds the reload value. when the tlx regis ter overflows from ffh to 00h , the tfx bit in tcon is set and tlx is reloaded with the contents of thx and the counting process continues from here. the reload operation leaves the contents of the thx register unchanged. this feature is best suitab le for u art baud rate generator f or it runs without continuous software intervention. note that only timer1 can be the baud rate source for uart. counting is enabled by the trx bit and proper setting of gate and intx pins. the functions of gate and intx pins are just the same as mode 0 and 1. 0 1 0 7 0 7 tfx th0 (th1) tl0 (tl1) interrupt t0oe t0/t1 (c/t =tmod.6) c/t =tmod.2 gate int0/int1 p1.2 (p0.7) tf0 (tf1) tr0/tr1 (t1oe) f sys 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) figure 10? 3 timer/counter 0 and 1 in mode 2 N79E845/844/8432 data s heet april 23 201 4 page 40 of 183 revision a2. 6 10.1.4 mode 3 ( two separate 8- bit timers) mode 3 has different operating methods for the two timers/counters . for timer/counter 1, mode 3 simply freezes the cou n- ter. timer/counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is show n in the following figure. tl0 uses the timer/counter 0 control bits t c/ , gate, tr0, int0 and tf0. the tl0 can be used to count clock cycles (clock/12 or clock/4) or 1 - to - 0 transi tions on pin t0 as determined by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, ti mer 1 can still be used in modes 0, 1 and 2, but its flexibility is somewhat limited. while its basic functionality is maintained, it no lon g- er has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and retains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can be also used as a baud rate generator for the serial port. 0 1 0 7 0 7 tf0 th0 tl0 interrupt t0=p1.2 c/t =tmod.2 gate=tmod.3 int0=p1.3 tr0=tcon.4 tr1=tcon.6 tf1 interrupt f sys 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) toggle (refer to mode 0) t0oe p1.2 pin p1.2 sfr toggle (refer to mode 0) t1oe p0.7 pin p0.7 sfr figure 10? 4 timer/counter 0 in mode 3 N79E845/844/8432 data s heet april 23 201 4 page 41 of 183 revision a2. 6 10.2 timer/counter 2 timer 2 is 1 6 - bit up counter cascaded with th2 , the upper 8 bits register, and tl2 , the lower 8 - bit register . equipped with rcomp2h and rcomp2l , timer 2 can operate under compare mode and auto - reload mode. the additional 3 - channel input capture module makes timer 2 detect and measure the width or period of input pulses. the results of 3 input ca p- tures are stores in c0h and c0l, c1h and c1l, c2h and c2l individually. the clock sourc e of timer 2 is from the clock system pre - scaled by a clock divider with 8 different scales for wide field application. the clock is enabled when tr2 ( t2con .2) is 1 , and disabled when tr2 is 0 . the following registers are related to timer 2 function. t2con ? timer 2 control (bit - addressable) 7 6 5 4 3 2 1 0 tf2 - - - - tr 2 - 2 rl cp/ r/w - - - - r/w - r/w address: c 8h reset value: 0000 0000b bit name description 7 tf 2 timer 2 o verflow f lag this bit is set when timer 2 overflows or a compare match occurs. if the timer 2 interrupt and the global interrupt are enable, setting this bit will make cpu execute timer 2 interrupt service routine. this bit is not automatically cleared via hardware and should be cleared via software. 6:3 - reserved 2 tr2 timer 2 r un c ontrol 0 = timer 2 is halted. clearing this bit will halt timer 2 and the current count will be preserved in th2 and tl2 . 1 = timer 2 is enabled. 1 - reserved 0 2 rl cp/ timer 2 capture or reload s elect ion this bit selects whether timer 2 functions in compare or auto - reload mode. 0 = auto - reload on timer 2 overflow or any input capture event. 1 = compare mode of timer 2. t2mod ? timer 2 mode 7 6 5 4 3 2 1 0 lden t2div[2:0] capcr compcr ldts[1:0] r/w r/w r/w r/w r/w r/w r/w r/w address: c 9h reset value: 0000 0000b bit name description 7 lden auto - reload enable . 0 = disable reloading rcomp2h and rcomp2l to th2 and tl2 on timer 2 overflow or any input capture event. 1 = en able reloading rcomp2h and rcomp2l to th2 and tl2 on timer 2 ove r flow or any input capture event . N79E845/844/8432 data s heet april 23 201 4 page 42 of 183 revision a2. 6 bit name description 6:4 t2 div[2:0] timer 2 c lock d ivider 0 00 = timer 2 clock divider is 1/4. 0 01 = timer 2 clock divider is 1/8. 0 10 = timer 2 clock divider is 1/16. 0 11 = timer 2 clock divider is 1/32. 100 = timer 2 clock divider is 1/64. 101 = timer 2 clock divider is 1/128. 110 = timer 2 clock divider is 1/256. 111 = timer 2 clock divider is 1/512. 3 capcr capture a uto - clear this bit enables auto - clear timer 2 value in th2 and tl2 when a determined i n- put capture event occurs. 0 = timer 2 continues counting when a capture event occurs. 1 = timer 2 value is auto - cleared as 0000h when a capture event occurs. 2 compcr compare m atch a uto - clear. this bit enables auto - clear timer 2 value in th2 and tl2 when a compare match occurs. 0 = timer 2 continues counting when a compare match occurs. 1 = timer 2 value is auto - cleared as 0000h when a compare match occurs. 1:0 ldts[1:0] auto - reload t rigger s elect ion these bits select the reload trigger event. 00 = reload when timer 2 overflows. 01 = reload when input capture 0 event occurs. 10 = reload when input capture 1 event occurs. 11 = reload when input capture 2 event occurs. rcom p2l ? timer 2 reload/compare low byte 7 6 5 4 3 2 1 0 rcomp2l [7:0] r/w address: c ah reset value: 0000 0000b bit name description 7:0 rcomp2l [7:0] timer 2 r eload/ c ompare l ow b yte th is register stores the low byte of compare value when timer 2 is configured in compare mode , i t holds the low byte of the reload value when auto - reload mode. rcomp2h ? timer 2 reload/compare high byte 7 6 5 4 3 2 1 0 rcomp2h [7:0] r/w address: c bh reset value: 0000 0000b bit name description 7:0 rcomp2h [7:0] timer 2 r eload/ c ompare h igh b yte th is register stores the high byte of compare value when timer 2 is confi g- ured in compare mode. and it holds the high byte of the reload value when auto - reload mode. N79E845/844/8432 data s heet april 23 201 4 page 43 of 183 revision a2. 6 tl2 ? timer 2 low byte 7 6 5 4 3 2 1 0 tl2 [7:0] r/w address: c c h reset value: 0000 0000b bit name description 7:0 tl2 [7:0] timer 2 l ow b yte the tl2 register is the low byte of the 16 - bit timer 2. th2 ? timer 2 high byte 7 6 5 4 3 2 1 0 th2 [7:0] r/w address: c d h reset value: 0000 0000b bit name description 7:0 th2 [7:0] timer 2 high byte the th2 register is the high byte of the 16 - bit timer 2. timer/counter 2 provides three operating mode which can be selected by control bits in t2con and t2mod as shown in the table below. note that the th2 and tl2 are accessed separately. it is strongly recommended that user stop timer 2 temporally for a reading from or writing to th2 and tl2 . the free - running reading or writing may cause unpredictable situation. N79E845/844/8432 data s heet april 23 201 4 page 44 of 183 revision a2. 6 table 10? 1 timer 2 operating modes timer 2 mode rl2 cp/ (t 2 con.0) lden (t 2 mod. 7 ) input capture 0 0 auto - reload 0 1 compare 1 x 10.2.1 input capture mode the input capture module with timer 2 implements the input capture mode. timer 2 should be configured by clearing 2 rl cp/ and lden bit to enter into input capture mode. the input capture module is configured through capcon0~2 registers. the input capture module supports 3 - c hannel inputs (ic0 and ic1 pins) that share i/o pin p 1.2 and p 0.7 . each input channel consists its own schmitt trigger input. the noise filter for each channel is enabled via setting enf0~ 1 (capcon2[ 5 :4]). it filters input glitches smaller than 4 cpu clocks. input capture 0~ 1 have independent edge detector but share with unique timer 2. the trigger edge is also configured individually by setting capcon1. it supports positive edge capture, negative edge capture, or both edge captures . each input capture channel h as its own enabling bit capen0~ 1 (capcon0[ 5 :4]). while any input capture channel is enabled and th e selected edge trigger occurs, the content of the free running timer 2 counter, th2 and tl2 , will be captured, transferred, and stores into the capture registers cnh and cnl. the edge trigge r- ing also causes capfn (capcon0.n) is set by hardware. the interr upt will be also generated if ecp tf (eie. 2 ) and ea bit are both set. for three input capture flags shares the same interrupt vector, the user should check capfn to confirm which channel comes the input capture edge , which flags should be cleared by softwar e. the bit capcr ( t2mod .3) benefits the implement of period calculation. setting capcr makes the hardware clear ti m- er 2 as 0000h automatically after the value of th2 and tl2 have been captured after an input capture edge event occurs. it eliminates the rou tine software overhead of writing 16 - bit counter or an arithmetic subtraction. N79E845/844/8432 data s heet april 23 201 4 page 45 of 183 revision a2. 6 tf2 timer 2 interrupt pre-scalar 1/4~1/512 f sys rcomp2h t2div[2:0] (t2mod[6:4]) rcomp2l th2 tl2 00 01 10 11 capf0 event capf1 event reserved lden (t2mod.7) ldts[1:0] (t2mod[1:0]) tr2 (t2con.2) timer 2 module c0h c0l noise filter enf0 (capcon2.4) or [00] [01] [10] cap0ls[1:0] (capcon1[1:0]) capen0 (capcon0.4) capf0 input capture 0 module input capture 1 module ic0 (p1.2) ic1 (p0.7) input capture flags capf[1:0] capcr (t2mod.3) capf0 event capf1 event clear timer 2 figure 10? 5 timer 2 input capture and auto - reload mode function block capcon0 ? input capture control 0 7 6 5 4 3 2 1 0 - - capen1 capen0 - - capf1 capf0 - - r/w r/w - - r/w r/w address: 92h reset value: 0000 0000b bit name description 7 :6 - reserved 5 capen1 input c apture 1 e nable 0 = disable i nput capture channel 1. 1 = enable i nput capture channel 1. 4 capen0 input c apture 0 e nable 0 = disable i nput capture channel 0. 1 = enable i nput capture channel 0. 3 :2 - reserved 1 capf1 input c apture 1 f lag this bit is set by hardware if the determined edge of input capture 1 occurs. this bit N79E845/844/8432 data s heet april 23 201 4 page 46 of 183 revision a2. 6 bit name description should cleared by software. 0 capf0 input c apture 0 f lag . this bit is set by hardware if the determined edge of input capture 0 occurs. this bit should cleared by software. capcon1 ? input capture control 1 7 6 5 4 3 2 1 0 - - - - cap1ls[1:0] cap0ls[1:0] - - - - r/w r/w r/w r/w address: 9 3 h reset value: 0000 0000b bit name description 7: 4 - reserved 3:2 cap1ls[1:0] input capture 1 l evel s elect ion 0 0 = falling edge. 0 1 = rising edge. 10 = either rising or falling edge. 11 = reserved 1:0 cap0ls[1:0] input c apture 0 l evel s elect ion 0 0 = falling edge. 0 1 = rising edge. 10 = either r ising or falling edge. 11 = reserved capcon2 ? input capture control 2 7 6 5 4 3 2 1 0 - - enf1 enf0 - - - - - - r/w r/w - - - - address: 9 4 h reset value: 0000 0000b bit name description 7 :6 - reserved 5 enf1 n oise f iler on i nput c apture 1 enable 0 = disable noise filter on input capture channel 1. 1 = enable noise filter on input capture channel 1. 4 enf0 n oise f iler on i nput c apture 0 enable 0 = disable noise filter on input capture channel 0. 1 = enable noise filter on input capture channel 0. 3:0 - reserved N79E845/844/8432 data s heet april 23 201 4 page 47 of 183 revision a2. 6 c0l ? capture 0 low byte 7 6 5 4 3 2 1 0 c0l[7:0] r/w address: e4h reset value: 0000 0000 b bit name description 7:0 c0l[7:0] input c apture 0 r esult l ow b yte the c0l register is the low byte of the 16 - bit result captured by input capture 0 . c0h ? capture 0 high byte 7 6 5 4 3 2 1 0 c0h[7:0] r/w address: e5h reset value: 0000 0000 b bit name description 7:0 c0h[7:0] input c apture 0 r esult h igh b yte the c0h register is the high byte of the 16 - bit result captured by input capture 0 . c1l ? capture 1 low byte 7 6 5 4 3 2 1 0 c1l[7:0] r/w address: e6h reset value: 0000 0000 b bit name description 7:0 c1l[7:0] input c apture 1 r esult l ow b yte the c1l register is the low byte of the 16 - bit result captured by input capture 1 . c1h ? capture 1 high byte 7 6 5 4 3 2 1 0 c1h[7:0] r/w address: e7h reset value: 0000 0000 b bit name description 7:0 c1h[7:0] input c apture 1 r esult h igh b yte the c1h register is the high byte of the 16 - bit result captured by input capture 1 . N79E845/844/8432 data s heet april 23 201 4 page 48 of 183 revision a2. 6 c2l ? capture 2 low byte 7 6 5 4 3 2 1 0 c2l[7:0] r/w address: edh reset value: 0000 0000 b bit name description 7:0 c2l[7:0] input c apture 2 r esult l ow b yte the c2l register is the low byte of the 16 - bit result captured by input capture 2. c2h ? capture 2 high byte 7 6 5 4 3 2 1 0 c2h[7:0] r/w address: eeh reset value: 0000 0000 b bit name description 7:0 c2h[7:0] input c apture 2 r esult h igh b yte the c2h register is the high byte of the 16 - bit result captured by input capture 2 . 10.2.2 auto - reload mode timer 2 can be configured as auto - reload mode by clearing 2 rl cp/ and setting lden bit. in this mode rcomp2h and rcomp2l registers stores the reload value. the contents in rcomp2h and rcom3l transfer into th2 and tl2 once the auto - reload event occurs. the event can be the timer 2 overflow or one of the triggering event on any of enabled input capture channel depending on the ldts[1:0] ( t2mod [1:0]) selection. note that once capcr (t2mod.3) is set, an input capture event only clears th2 and tl2 without reloading rcomp2h and rcomp2l contents. 10.2.3 compare mode timer 2 can be als o configured simply as the compare mode by setting 2 rl cp/ . in this mode rcomp2h and rcomp2l registers serve as the compare value registers. as timer 2 up counting, th2 and tl2 match rcomp2h and rcomp2l , tf3 ( t2con .7) will be set by hardware to indicate a compare match event. setting compcr ( t2mod .2) makes the hardware to clear timer 2 counter as 0000h automatically after a compare match has occurred. N79E845/844/8432 data s heet april 23 201 4 page 49 of 183 revision a2. 6 tf2 timer 2 interrupt pre-scalar 1/4~1/512 f sys rcomp2h t2div[2:0] (t2mod[6:4]) rcomp2l th2 tl2 tr2 (t2con.2) timer 2 module compcr (t2mod.2) clear timer 2 = figure 10? 6 timer 2 compare mode function block N79E845/844/8432 data s heet april 23 201 4 page 50 of 183 revision a2. 6 11 watchdog timer (wdt) the N79E845/844/8432 provides one watchdog counter to serve as a system monitor, which improve the reliability of the system. watchdog timer is useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. the periodic interrupt of watchdog timer can also serve as an event timer or a durational system supervisor in a monito r- ing system which generally opera tes in idle or power - down mode . the watchdog timer is basic a setting of divider that divides an internal low speed clock source. the divider output is selectable and determines the time - out interval. when the time - out interval is fulfilled, it will wake t he system up from idle or power - down mode and an interrupt event will occur. if watchdog timer reset is enabled, a system reset will occur after a period of delay if without any software response. wps2,wps1,wps0 select 1/2 1/1 1/128 1/256 1/64 1/32 1/16 1/8 pre-scalar internal osc (10khz) enwdt wdtf delay 512 clock (internal 10khz) wclr clock (written '1' by software) ewrst 6-bit counter .... clear wdt counter overflow checking overflow 000 001 010 011 100 101 110 111 1: on 0: off fwck: wdt clock wdt interrupt ewdi wdt reset wrf (eie.4) idl (pcon.0) pd (pcon.1) widpd figure 11-1 watchdog timer 11.1 functional description the watchdog timer should first be reset 00h by using wdclr(wdcon0.6) to ensure that the timer starts from a known state. after disable watchdog timer through clearing wdten (wdcon 0 .7) will also clear this counter. the wdclr bit is used to reset the watchdog timer. this bit is self - cleared thus the user doesn?t need to clear it. after wri t- ing 1 to wdclr, the hardware will automatically clear it. after wdten set as 1, the watchdog tim er starts counting. the time - out interval is selected by the three bits wps2, wps1, and wps0 (wdcon0[2:0]). when the selected time - out occurs, the watchdog timer will set the interrupt flag wdtf (wdcon0.5). the watchdog timer interrupt enable bit locates a t eie .4 register. if watchdog timer reset is enabled by writing logic 1 to ewrst (wdcon1.0) bit. an add i- tional 512 clocks of the low speed internal rc delays to expect a counter clearing by setting wdclr. if these is no wdclr setting during this 512 - clock period, a reset will happen. once a reset due to watchdog timer occurs, the watchdog timer reset flag wdtrf (wdcon0.3) will be set. this bit keeps unchanged after any reset other than a po w- er - on reset. the user may clear wdtrf via software. in general, sof tware should restart the counter to put it into a known N79E845/844/8432 data s heet april 23 201 4 page 51 of 183 revision a2. 6 state by setting wdclr. the watchdog timer also provides a widpd bit (wdcon 0 .4) to allow the watchdog timer continuing running after the system enters into idle or power down operating mode. the hardw are automatically clears wdt counter after entering into or being woken - up from idle or power - down mode . it prevents unconscious system reset. wdcon0 ? watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdten wdclr wdtf widpd wdtrf wps2 wps1 wps0 r/w w r/w r/w r/w r/w r/w r/w address: d8h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7 wdten wdt e na ble wdten is initialized by inverted cwdten (config3, bit - 7) at any other resets. 0 = disable wdt at power - on reset. 1 = enable wdt at power - on reset. 6 wdclr wdt c ounter c lear writing ?1? to clear the wdt counter to 0000h. note that this bit is written - only and has no need to be cleared by being written ?0?. 5 wdtf wdt i nterrupt f lag this bit will be set by hardware when wdt counter overflows. 4 widpd w dt r unning in i dle and power -d own m ode this bit decides whether watchdog timer runs in idle or power - down mode . 0 = wdt counter is halted while cpu is in idle or power - down mode . 1 = wdt keeps running while cpu is in idle or power - down mode . N79E845/844/8432 data s heet april 23 201 4 page 52 of 183 revision a2. 6 bit name description 3 wdtrf wdt r eset f lag when the mcu resets itself, this bit is set by hardware. the bit should be cleared by sof t- ware. if ewrst = 0, the interrupt flag wdtf won?t be set by hardware, and the mcu will reset itself right away. if ewrst = 1, the interrupt flag wdtf will be set by hardware and the mcu will jump into wdt?s interrupt service routine if wdt interrupt is enabled, and the mcu won?t reset itself until 512 cpu clocks elapse. in other words, in this condition, the user also needs to clear the wdt counter (by writi ng ?1? to wdclr bit) during this period of 512 cpu clocks, or the mcu will also reset itself when 512 cpu clocks elapse. 2:0 wps[2:0] wdt p re- scalar s elect ion use these bits to select wdt time - out period. the wdt time - out period is determined by the formula ) escalar pr f ( 64 = wck , where fwck is the frequency of the wdt clock source. the following table shows an example of wdt timeout period for different fwck. [1] wdten is initialized by reloading the inversed value of cwdten ( config3 .7) after all re sets. [2] widpd and wps[2:0] are cleared after power - on reset and keep unchanged after any other resets. [3] wdtrf will be cleared after power - on reset, be set after watchdog timer reset, and remains unchanged after any other resets. wdcon1 ? watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - ewrst - - - - - - - r/w address: ab h reset value: 0000 0000b bit name description 0 ewrst 0 = d isable wdt reset funct i on. 1 = e nable wdt reset funct i on. [1] ewrst is cleared after power - on reset and keeps unchanged after any other resets. the watchdog time - out interval is determined by the formula ) escalar pr f ( 64 = wck . where f wck is the frequency of inte r- nal 10 khz rc. the following table shows an example of the watchdog time - out interval under different f wck and pre - scalars. N79E845/844/8432 data s heet april 23 201 4 page 53 of 183 revision a2. 6 eie ? extensive interrupt enable 7 6 5 4 3 2 1 0 et2 espi epwm ewdi - ecptf ekb ei2 c r/w r/w r/w r/w - r/w r/w r/w address: e8h reset value: 0000 0000b bit name description 4 ewdi 0 = d isable watchdog timer interrupt. 1 = e nable watchdog timer interrupt. the watchdog timer time - out selection will result in different time - out values depending on the clock speed. the reset, when enabled, will occur when 512 clocks after time - out has occurred. table 11- 1 time - out v alues for the watchdog t imer (wps2,wps1,wps0) pre -s cal a r wdt interrupt time -out reset time -out number of clocks time number of clocks time (0,0,0) 1/1 2 6 6.4ms 2 6 +512 57.6ms (0,0,1) 1/2 2x 2 6 12.8ms 2x 2 6 +512 64ms (0,1,0) 1/8 8x 2 6 51.2ms 8x 2 6 +512 102.4ms (0,1,1) 1/16 16x 2 6 102.40ms 16x 2 6 +512 153.6ms (1,0,0) 1/32 32x 2 6 204.80ms 32x 2 6 +512 256ms (1,0,1) 1/64 64x 2 6 409.60ms 64x 2 6 +512 460.8ms (1,1,0) 1/128 128x 2 6 819.20ms 128x 2 6 +512 870.4ms (1,1,1) 1/256 256x 2 6 1.638s 256x 2 6 +512 1.6892s 11.2 applications of watchdog timer reset the main application of the watchdog timer with time - out reset enabling is for the system monitor. this is important in real - time control applications. in case of some power glitches or electro - magnetic interference, th e processor may begin to execute erroneous codes and operate in an unpredictable state. if this is left unchecked the entire system may crash. using the watchdog timer during software development will require the user to select ideal watchdog reset locatio ns for inser t- ing instructions to reset the watchdog timer. by inserting the instruction setting wdclr, it will allow the code to run without any watchdog timer reset. however if any erroneous code executes by any power of other interference, the i n- N79E845/844/8432 data s heet april 23 201 4 page 54 of 183 revision a2. 6 structio ns to clear the watchdog timer counter will not be executed at the required instants. thus the watchdog timer reset will occur to reset the system start from an erroneously executing condition. the user should remember that wdcon 0 requires a timed access w riting. 11.3 applications of watchdog timer interrupt there is another application of the watchdog timer, which is used as a simple timer. the wdtf flag will be set while the watchdog timer completes the selected time interval. the software polls the wdtf flag to detect a time - out and the wdclr allows software to restart the timer. the watchdog timer can be also used as a very long timer. every time the time - out occurs, an interrupt will occur if the individual interrupt ewd i (eie.4) and global interrupt enable ea is set. in some application of low power consumption, the cpu usually stays in idle mode when nothing needs to be served to save power consumption. after a while the cpu will be woken up to check if anything needs to be served at an interval of programm ed period implemented by timer 0, 1 or 2. however, the current consumption of idle mode still keeps at a ma level. to further reducing the current consumption to a level, the cpu should stay in power - down mode when nothing needs to be served, and has the ability of waking up at a programmable interval. the N79E845/844/8432 is equipped with this useful function. it provides a very low power internal rc 10 khz . along with the low power consum p- tion application, the watchdog timer needs to count under idle and power - down mode and wake cpu up from idle or power - down mode . the demo code to accomplish this feature is shown below. the demo code of watchdog timer waking cpu u p from power down. org 0000h ljmp start org 0053h ljmp wdt_isr org 0100h wdt_isr: clr ea mov ta,#0aah mov ta,#55h orl wdcon0,#01000000b ;clear watchdog timer counter inc acc mov p0,acc setb ea clr ea mov ta,#0aah mov ta,#55h anl wdcon0,#11011111b ;clear watchdog timer interrupt flag setb ea reti start: mov ta,#0aah mov ta,#55h orl wdcon0,#01000000b ;clear watchdog timer counter N79E845/844/8432 data s heet april 23 201 4 page 55 of 183 revision a2. 6 mov ta,#0aah mov ta,#55h orl wdcon0,#10000000b ;enable watchdog timer to run check_clear: mov a,wdcon0 jb acc.6,check_clear mov ta,#0aah mov ta,#55h orl wdcon0,#00000111b ;choose interval length mov ta,#0aah mov ta,#55h anl wdcon1,#11111110b ;disable watchdog timer reset setb ewdi ;enable watchdog timer interrupt mov ta,#0aah mov ta,#55h setb widpd setb ea ;******************************************************************** ;enter into power-down mode ;******************************************************************** loop: orl pcon,#02h ljmp loop end N79E845/844/8432 data s heet april 23 201 4 page 56 of 183 revision a2. 6 12 serial port (uart) the N79E845/844/8432 include s one enhanced full duplex serial port with automatic address recognition and framing error detection. the serial port supports three modes of full duplex uart (universal asynchronous receiver and tran s- mitter) in mode 1, 2, and 3. this means it can transmit and receive simultaneously. the serial port is also receiving - buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. the receiving and transmitting registers are both access ed at sbuf. writing to sbuf loads the transmitting re g- ister, and reading sbuf accesses a physically separate receiving register. there are four operation modes in serial port. in all four modes, transmission initiates by any instruction that uses sbuf as a destination register. note that before serial port function works, the port latch bits of rx d and txd pins have to be set to 1. scon ? serial port control (bit - addressable) 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri r/w r/w r/w r/w r/w r/w r/w r/w address: 98h reset value: 0000 0000b bit name description 7 sm0/fe serial p ort m ode s elect ion smod0 (pcon.6) = 0: see table 12 ? 1 serial port mode description for details. smod0 (pcon.6) = 1: sm0/fe bit is used as frame error (fe) status flag. 0 = frame error (fe) does not occur. 1 = frame error (fe) occurs and is detected. 6 sm1 5 sm2 multiprocessor c ommunication m ode e nable the function of this bit is dependent on the serial port mode. mode 0: this bit select the baud rate between f sys /12 and f sys /4. 0 = the clock runs at f sys /12 baud rate. it maintains standard 8051 compatibility. 1 = the clock runs at f sys /4 baud rate for faster serial communication. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the received stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is valid only when the received 9 th bit is logic 1 and the received data matches given or broadcast address. N79E845/844/8432 data s heet april 23 201 4 page 57 of 183 revision a2. 6 bit name description 4 ren receiving e nable 0 = serial port reception is disabled. 1 = serial port reception is enabled in mode 1,2, and 3. in mode 0, clearing and then s etting ren initiate s one - byte reception . after reception is complete, this bit will not be cleared via hardware. the user should clear and set ren again via software to triggering the next byte reception. 3 tb8 9 th t ransmitted b it this bit defines the state of the 9 th transmission bit in serial port mode 2 and 3. it is not used in mode0 and 1. 2 rb8 9 th r eceived b it the bit identifies the logic level of the 9 th received bit in modes 2 and 3. in mode 1, if sm2 0, rb8 is the logic level of the received stop bit. rb8 is not used in mode 0. 1 ti transmission i nterrupt f lag this flag is set via hardware when a byte of data has been transmitted by the uart after the 8 th bit in mode 0 or the last bit of data in other modes. when the uart interrupt is enabled, setting this bit causes the cpu to execute the uart int errupt service routine. this bit should be cleared manually via software. 0 ri receiving i nterrupt f lag this flag is set via hardware when a 8 - bit or 9 - bit data has been received by the uart after the 8 th bit in mode 0, after sampling the stop bit in mode 1, or after sampling the 9 th bit in mode 2 and 3. sm2 bit has restriction for exception. when the uart interrupt is enabled, setting this bit causes the cpu to execute to the uart interrupt service routine. this bit should be cleared manually via software . table 12? 1 serial port mode description mode sm0 sm1 description frame bits baud rate 0 0 0 synchronous 8 f sys divided by 12 or by 4 [1] 1 0 1 asynchronous 10 timer 1 overflow rate divided by 32 or divided by 16 [2] 2 1 0 asynchronous 11 f sys divided by 64 or 32 [2] 3 1 1 asynchronous 11 timer 1 overflow rate divided by 32 or divided by 16 [2] [1] while sm2 (scon.5) is logic 1. [2] while smod (pcon.7) is logic 1. pcon ? power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7 smod serial p ort d ouble b aud r ate e nable setting this bit doubles the serial port baud rate in uart mode 2 and mode 1 or 3 only if timer 1 overflow is used as the baud rate source. see table 12? 1 serial port mode description for details. N79E845/844/8432 data s heet april 23 201 4 page 58 of 183 revision a2. 6 bit name description 6 smod0 framing e rror d etection e nable 0 = framing error detection is disabled. sm0/fe (scon.7) bit is used as sm0 as standard 80c51 function. 1 = framing error detection is enabled. sm0/fe bit is used as frame error (fe) status fla g. sbuf ? serial data buffer 7 6 5 4 3 2 1 0 sbuf[7:0] r/w address: 99h reset value: 0000 0000b bit name description 7:0 sbuf[7:0] serial d ata b uffer this byte actually consists two separate registers. one is the receiving resister, and the other is the transmitting buffer. when data is moved to sbuf, it goes to the transmitting buffer and is shifted for serial transmission. when data is moved from sbuf, it comes from the receiving buffer. the transmission is initiated throu gh moving a byte to sbuf. 12.1 mode 0 mode 0 provides synchronous communication with external devices. serial data enters and exits through rxd pin. txd outputs the shift clock. 8 bits are transmitted or received. mode 0 therefore provides half - duplex communication because the transmitting or receiving data is via the same data line rxd. the baud rate is enhanced to be selected as f sys /12 if sm2 (scon.5) is 0 or as f sys /4 if sm2 is 1. note that whenever transmitting or receiving, the serial clock is alw ays ge n- erated by the microcontroller. thus any device on the serial port in mode 0 should accept the microcontroller as the ma s- ter. figure 12? 1 shows a simplified functional diagram of the serial port in mode 0 and associated timing. N79E845/844/8432 data s heet april 23 201 4 page 59 of 183 revision a2. 6 figure 12? 1 serial port mode 0 function block N79E845/844/8432 data s heet april 23 201 4 page 60 of 183 revision a2. 6 as shown there is one bidirectional data line (rxd) and one shift clock line (txd). the shift clock is used to shift data in or out of the serial port controller bit by bit for a serial communication. data bits enter or exit lsb first. the band rate is equ al to the shift clock frequency. transmission is initiated by any instruction writes to sbuf. the control block will then shift out the clock and begin to transfer data until all 8 bits are complete. then the transmitted flag ti (scon.1) will be set 1 to i ndicate one byte tran s- mitting complete. reception is initiated by clearing and then setting ren (scon.4) while ri (scon..0) is 0. this condition tells the serial port controller that there is data to be shifted in. this process will continue until 8 bits h ave been received. then the r e- ceived flag ri will be set as 1. note that ren will not be cleared via hardware. the user should first clear ri, clear ren and then set ren again via software to triggering the next byte reception. 12.2 mode 1 mode 1 supports async hronous, full duplex serial communication. the asynchronous mode is commonly used for co m- munication with pcs, modems or other similar interfaces. in mode 1, 10 bits are transmitted (through txd) or received (through rxd) including a start bit (logic 0), 8 data bits (lsb first) and a stop bit (logic 1). the baud rate is determined by the timer 1. smod (pcon.7) setting 1 makes the baud rate double while timer 1 is selected as the clock source. fi g- ure 12 ? 2 shows a simplified funct ional diagram of the serial port in mode 1 and associated timings for transmitting and receiving. N79E845/844/8432 data s heet april 23 201 4 page 61 of 183 revision a2. 6 figure 12 ? 3 serial port mode 1 function block and timing diagram N79E845/844/8432 data s heet april 23 201 4 page 62 of 183 revision a2. 6 transmission is initiated by any writing instructions to sbuf. transmission takes place on txd pin. first the start bit comes out, the 8 - bit data follows to be shifted out and then ends with a stop bit. after the stop bit appears, ti (scon.1) will be set to indicate one byte transmission complete. all bits are s hifted out depending on the rate determined by the baud rate generator. once the baud rate generator is activated and ren (scon.4) is 1, the reception can begin at any time. reception is init i- ated by a detected 1 - to - 0 transition at rxd. data will be sample d and shifted in at the selected baud rate. in the midst of the stop bit, certain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either sm2 (scon.5) = 0, or the received stop bit = 1 while sm2 = 1. if these conditi ons are met, the sbuf will be loaded with the received data, the rb8 (scon.2) with stop bit, and ri will be set. if these conditions fail, there will be no data loaded and ri will remain 0. after above receiving progress, the seri al control will look forwa rd another 1 - 0 transition on rxd pin to start next data reception. 12.3 mode 2 mode 2 supports asynchronous, full duplex serial communication. different from mode1, there are 11 bits to be transmi t- ted or received. they are a start bit (logic 0), 8 data bits (ls b first), a programmable 9 th bit tb8 or rb8 bit and a stop bit (logic 1). the most common use of 9 th bit is to put the parity bit in it. the baud rate is fixed as 1/32 or 1/64 the clock sy s- tem frequency depending on smod bit. figure 12? 4 shows a simplified functional diagram of the serial port in mode 2 and associated timings for transmitting and receiving. N79E845/844/8432 data s heet april 23 201 4 page 63 of 183 revision a2. 6 figure 12? 4 serial port mode 2 function block and timing diagram N79E845/844/8432 data s heet april 23 201 4 page 64 of 183 revision a2. 6 transmission is initiated by any writing instructions to sbuf. transmission takes place on txd pin. first the start bit comes out, the 8 - bit data and bit tb8 (scon.3) foll ows to be shifted out and then ends with a stop bit. after the stop bit appears, ti will be set to indicate the transmission complete. while ren is set, the reception is allowed at any time. a falling edge of a start bit on rxd will initiate the reception pr o- gress. data will be sampled and shifted in at the selected baud rate. in the midst of the 9 th bit, certain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either sm2(scon.5) = 0, or the received 9 th bit = 1 while sm2 = 1. if these conditions are met, the sbuf will be loaded with the received data, the rb8(scon.2) with tb8 bit and ri will be set. if these conditions fail, there will be no data loaded and ri will remain 0. after above receiving progress, the seri al control will look forward another 1 - 0 transition on rxd pin to start next data reception. 12.4 mode 3 mode 3 has the same operation as mode 2, except its baud rate clock source. as shown is figure 12? 5 , mode 3 uses ti m- er 1 overflow as its baud rate clock. N79E845/844/8432 data s heet april 23 201 4 page 65 of 183 revision a2. 6 figure 12? 5 serial port mode 3 function block N79E845/844/8432 data s heet april 23 201 4 page 66 of 183 revision a2. 6 12.5 baud rates table 12? 2 uart baud rate formulas uart m ode baud r ate c lock s ource baud r ate 0 oscillator 12 / f sys or 4 / f sys [1] 2 oscillator sys smod f 64 2 1 or 3 timer/counter 1 overflow [2] ( ) 1 th 256 12 f 32 2 sys smod ? or ( ) 1 th 256 4 f 32 2 sys smod ? [3] [1] while sm2 (scon.5) is set as logic 1 . [2] timer 1 is configured as a timer in auto - reload mode (mode 2). [3] while t1m (ckcon.4) is set as logic 1 . note that in using timer 1 as the baud rate generator, the interrupt should be disabled. the timer itself can be configured for either ?timer? or ?counter? operation. and timer 1 can be in any of its 3 running modes. in the most typical applic a- tions, it is configured for ?timer? operation, in the auto - reload mode (mode2). if timer 1 is used as the baud rate gener a- tor, the reloaded value is stored in th1. therefore the baud rate is determined by th1 value. table 12 ? 3 lists various commonly used baud rates and how they can be obtained from timer 1. in this mode, timer 1 operates with divided - by - 12 pre - scale, as an auto - reload timer with smod (pcon.7) is 0. if smod is 1, the baud rate will be doubled. table 12? 3 timer 1 generated commonly used baud rates th1 reload value oscillator frequency (mhz) baud rate 11.0592 14.7456 18.432 22.1184 57600 ffh 38400 ffh 19200 feh fdh 9600 fdh fch fbh fah 4800 fah f8h f6h f4h 2400 f4h f0h ech e8h 1200 e8h e0h d8h d0h 300 a0h 80h 60h 40h N79E845/844/8432 data s heet april 23 201 4 page 67 of 183 revision a2. 6 12.6 framing error detection framing error detection is provided for asynchronous modes. (mode 1, 2 and 3.) the framing error occurs when a valid stop bit is not detected due to the bus noise or contention. the uart can detect a framing error and notify the software. the framing error bit, fe, is located in scon.7. this bit normally serves as sm0. while the framing error detectio n en a- ble bit smod0 (pcon.6) is set 1, it serves as fe flag. actually sm0 and fe locate in different registers. the fe bit will be set 1 via hardware while a framing error occurs. it should be cleared via software. note that smod0 should be 1 while reading or writing to fe. if fe is set, any of the f ollowing frames received without any error will not clear the fe flag. the clearing has to be done via software. 12.7 multiprocessor communication the communication feature of the N79E845/844/8432 enables a master device send a multiple frame serial message to a slave device in a multi - slave configuration. it does this without interrupting other slave devices that may be on the same serial line. uart mode 2 or 3 mode can use t his feature only . after 9 data bits are received. the 9 th bit value is written to rb8 (scon.2). the user can enable this function by setting sm2 (scon.5) as logic 1 so that when the stop bit is r e- ceived, the serial interrupt will be generated only if rb8 is 1. when the sm2 bit i s 1, serial data frames that are received with the 9 th bit as 0 do not generate an interrupt. in this case, the 9 th bit simply separates the address from the serial data. when the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an a d- dress byte to identify the target slave. note that in this case, an address byte differs from a data byte: in an address byte , the 9 th bit is 1 and in a data byte, it is 0. the address byte interrupts all slaves so th at each slave can examine the received byte and see if it is being addressed. the addressed slave then clears its sm2 bit and prepares to receive incoming data bytes. the sm2 bits of slaves that were not addressed remain set, and they continue operating no rmally while ignoring the incoming data bytes. follow the steps below to configure multiprocessor communications: 1. set all devices (masters and slaves) to uart mode 2 or 3. 2. write the sm2 bit of all the slave devices to 1. 3. the master device's transm ission protocol is: ? first byte: the address, identifying the target slave device, (9 th bit = 1). ? next bytes: data, (9 th bit = 0). N79E845/844/8432 data s heet april 23 201 4 page 68 of 183 revision a2. 6 4. when the target slave receives the first byte, all of the slaves are interrupted because the 9 th data bit is 1. the targete d slave compares the address byte to its own address and then clears its sm2 bit to receiving incoming data. the other slaves continue operating normally. 5. after all data bytes have been received, set sm2 back to 1 to wait for next address. sm2 has no ef fect in mode 0, and in mode 1 can be used to check the validity of the stop bit. for mode 1 reception, if sm2 is 1, the receiving interrupt will not be issue unless a valid stop bit is received. 12.8 automatic address recognition the automatic address recogniti on is a feature which enhances the multiprocessor communication feature by allowing the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminat ing the need for the software to examine every serial address which passes by the serial port. only when the serial port recognizes its own address, the receiver sets ri bit to request an inte r- rupt. the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled. (sm2 is set.) if desired, the user may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. ri is set only when the rece ived command frame address matches the device?s a d- dress and is terminated by a valid stop bit. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the ?given? slave address or addre sses. all of the slaves may be contacted by using the ?broadcast? address. two sfrs are used to define the slave address, saddr, and the slave address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are ?don?t car e?. the saden mask can be logically anded with the saddr to create the ?given? address which the master will use for addressing each of the slaves. use of the ?given? address allows multiple slaves to be recognized while excluding others. saddr ? slave add ress 7 6 5 4 3 2 1 0 saddr[7:0] r/w address: a9h reset value: 0000 0000b bit name description 7:0 saddr[7:0] slave a ddress. this byte specifies the microcontroller?s own slave address for uart multipr o- cessor communication. N79E845/844/8432 data s heet april 23 201 4 page 69 of 183 revision a2. 6 saden ? slave address mask 7 6 5 4 3 2 1 0 saden[7:0] r/w address: b9h reset value: 0000 0000b bit name description 7:0 saden[7:0] slave a ddress m ask. this byte is a mask byte that contains ?don?t - care? bits (defined by zeros) to form the device?s given address. the don?t - care bits provide the flexibility to address one or more slaves at a time. the following examples will help to show the versatility of this scheme. example 1, slave 0: saddr = 11000000b saden = 11111101b given = 110000x0b example 2, slave 1: saddr = 11000000b saden = 11111110b given = 1100000xb in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires 0 in bit 0 and it ignores bit 1. slave 1 requires 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010b since slave 1 requires 0 in bit 1. a unique address for slave 1 would be 11000001b since 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for sl ave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 11000000b. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: example 1, slave 0: saddr = 11000000b saden = 11111001b given = 11000xx0b example 2, slave 1: saddr = 11100000b saden = 11111010b given = 11100x0xb example 3, slave 2: saddr = 11000000b saden = 11111100b N79E845/844/8432 data s heet april 23 201 4 page 70 of 183 revision a2. 6 given = 110000xxb in the above example the differentiation among the 3 slaves is in the lower 3 address bits. sla ve 0 requires that bit 0 = 0 and it can be uniquely addressed by 11100110b. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 11100101b. slave 2 requires that bit 2 = 0 and its unique address is 11100011b. to select slaves 0 and 1 and exc lude slave 2 use address 11100100b, since it is necessary to make bit 2 = 1 to exclude slave 2. the ?broadcast? address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as ? don?t care ?. in most cases, interpreting the ? don?t care ? as ones, the broadcast address will be ffh. on reset, saddr and saden are initialized to 00h. this produces a ?given? address of all ? don?t care ? as well as a ?broadcast? address of all xxxxxxxxb (all ?don?t care? bits). this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. N79E845/844/8432 data s heet april 23 201 4 page 71 of 183 revision a2. 6 13 serial peripheral interface (spi) 13.1 features the N79E845/844/8432 exists a serial peripheral interface (spi) block to support high - speed serial communication. spi is a full - duplex, high - speed , synchronous communication bus between mcus or other peripheral devices such as serial eeprom, lcd driver, or d/a converter. it provides either master or slave mode, high - s peed rate up to f sys / 16 for ma s- ter mode and f sys /4 for slave mode , transfer complete and write collision flag. for a multi - master system, spi supports master mode fault to protect a multi - master conflict . 13.2 functional description divider /16, /32, /64, /128 select 8-bit shift register read data buffer msb lsb pin contorl logic miso mosi spclk ss spi status control logic spi status register spi control register clock logic s m m s clock spif wcol spiovf modf dismodf spi interrupt request spien mstr mstr ssoe dismodf spr0 spr1 spr0 spr1 cpha cpol mstr lsbfe spien ssoe spien internal data bus f sys figure 13? 1 spi block d iagram figure 13? 1 shows spi block diagram and provides an overview of spi architecture in this device. the main blocks of spi are the spi control register logic , spi status logic, clock rate control logic, and pin control logic . for a serial data transfer N79E845/844/8432 data s heet april 23 201 4 page 72 of 183 revision a2. 6 or receiving, the spi block exists a shift register and a read data buffer. it is single buffered in the transmit direction and double buffered in the receiv ing d irection. transmit data cannot be written to the shifter until the previous transfer is co m- plete. receiv ing logic consist s of parallel read data buffer so the shift r egister is free to accept a second data, as the first received data will be transferred to the read data buffer. the four pins of spi interface are master - in/slave - out (miso), master - out/slave - in (mosi), shift clock (s pcl k), and slave select ( ss ). the mosi pin is used to transfer a 8 - bit data in series from the master to the slave. therefore, mosi is an output pin for master device and a input for slave. respectively , the miso is used to receive a serial dat a from the slave to the master. the spclk pin is the clock output in master mode, but is the clock inp ut in slave mode. the shift clock is used to sy n- chronize the data movement both in and out of the devices through their mosi and miso pins. the shift clock is driven by the master mode device for eight clock cycles which exchanges one byte data on the seri al lines. for the shift clock is always produced out of the master device, the system should never exist more than one device in master mode for avoi d- ing device conflict. it is strongly recommended that t he schmitt trigger input buffer be enabled. each sla ve peripheral is selected by one slave select pin ( ss ). the signal should stay low for any slave access. when ss is driven high, the slave device will be inactivated. if the system is multi - slave, there should be onl y one slave d e- vice selected at the same time. in the master mode mcu , the ss pin does not function and it can be configured as a ge n- eral purpose i/o. however, ss can be used as master mode fault detection (s ee section 13.7 ? mode fault detection ? ) via software setting if multi - master environment exists. the N79E845/844/8432 also provide auto - activating function to toggle ss between each byte - transfer. miso mosi spclk ss i/o port 0 1 3 i/o port 0 1 3 so si sck ss slave device 1 master/slave mcu1 miso mosi spclk ss master/slave mcu2 so si sck ss slave device 2 so si sck ss slave device 3 figure 13? 2 spi multi - master, multi - slave interconnection N79E845/844/8432 data s heet april 23 201 4 page 73 of 183 revision a2. 6 figure 13? 2 shows a typical interconnection of spi devices. the bus gener ally connects devices together through three signal wires, mosi to mosi, miso to miso, and s p c l k to s p c l k. the master devices select the individual slave devices by using four pins of a parallel port to control the four ss pins. mcu1 and mcu2 play either master or slave mode. the ss should be configured as master mode fault detection to avoid multi - master conflict. spi clock generator miso miso mosi mosi spclk spclk v ss ss ss 7 6 5 4 3 2 1 0 spi shift register 7 6 5 4 3 2 1 0 spi shift register master mcu slave mcu * * ss configuration follows dismodf and ssoe bits. figure 13? 3 spi single - master, single - slave interconnection figure 13? 3 shows the simplest spi system interconnection, single - master and signal - slave. during a t ransfer, the master shifts data out to the slave via mosi line. while simultaneously, the master shifts data in from the slave via miso line. the two shift registers in the master mcu and the slave mcu can be considered as one 16 - bit circular shift registe r. therefore, while a transfer data pushed from master into slave, the data in slave will be also pulled in master device r e- spectively. the transfer effectively exchanges the data which was in the spi shift registers of the two mcus. by default , spi data is transferred msb first. if the lsbfe (spcr.5) is set, spi data shifts lsb first. this bit does not affect the position of the msb and lsb in the data register. note that all following description and figures are under the condition of lsbfe logic 0. msb is transmitted and received first. 13.3 spi control registers there are three spi registers to support its operations, they are spi control register (spcr) , spi status register (spsr) , and spi data register (spdr) , which registers provide control, status, data storage functions , and clock rate selection. the following regis ters relate to spi function. N79E845/844/8432 data s heet april 23 201 4 page 74 of 183 revision a2. 6 spcr ? serial peripheral control register 7 6 5 4 3 2 1 0 ssoe spien lsbfe mstr cpol cpha spr1 spr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f3 h reset value: 0000 0000b bit name description 7 ssoe slave s elect o utput e nable this bit is used in combination with the dismodf (spsr.3) bit to determine the feature of ss pin . this bit takes effect only under mstr = 1 and dismodf = 1 condition. 0 = ss functions as a general purpose i/o pin. 1 = ss automatically goes low for each transmission when selecting external slave device and goes high during each idle state to de - select the slave device. 6 spien spi e nable 0 = disable spi function. 1 = enable spi function. 5 lsbfe lsb f irst e nable 0 = the spi data is transferred msb first. 1 = the spi data is transferred lsb first. 4 mstr master m ode e nable this bit switches the spi operating between master and slave modes. 0 = the spi is configured as slave mode. 1 = the spi is configured as master mode. 3 cpol spi c lock p olarity s elect ion cpol bit determines the idle state level of the spi clock. refer to figure 13 ? 4 spi clock format 0 = spi clock is low in idle state. 1 = spi clock is high in idle state. N79E845/844/8432 data s heet april 23 201 4 page 75 of 183 revision a2. 6 bit name description 2 cpha spi clock phase select cpha bit determines the data sampling edge of the spi clock. see figure 13 ? 4 spi clock format . 0 = the data is sampled on the first edge of the spi clock. 1 = the data is sampled on the second edge of the spi clock. 1 spr1 spi c lock r ate s elect ion the two bits select four grades of spi clock divider. spr 1 spr 0 divider spi clock rate 0 0 16 1.25m bit/s 0 1 32 625k bit/s 1 0 64 312k bit/s 1 1 128 156k bit/s the clock rates above are illustrated under f sys = 20 mhz condition. 0 spr0 table 13? 1 slave select pin configuration dismodf ssoe master mode (mstr = 1) slave mode (mstr = 0) 0 x ss input for mode fault ss input for slave select 1 0 general purpose i/o 1 1 automatic ss output spsr ? serial peripheral status register 7 6 5 4 3 2 1 0 spif wcol spiovf modf dismodf - - - r/w r/w r/w r/w r/w - - - address: f4h reset value: 0000 0000b bit name description 7 spif spi c omplete f lag this bit is set to logic 1 via hardware while an spi data transfer is complete or an receiving data has been moved into the spi read buffer. if espi (eie .6) and ea are enabled, an spi interrupt will be required. this bit should be cleared via sof t- ware. at tempting to write to spdr is inhibited if spif is set. 6 wcol write c ollision e rror f lag this bit indicates a write collision event. once a write collision event occurs, this bit will be set. it should be cleared via software. N79E845/844/8432 data s heet april 23 201 4 page 76 of 183 revision a2. 6 bit name description 5 spiovf spi o verrun e rror f lag this bit indicates an overrun event. once an overrun event occurs, this bit will be set. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. 4 modf mode f ault e rror f lag this bit indicates a mode fault error event. if ss pin is configured as mode fault input (mstr = 1 and dismodf = 0) and ss is pulled low by external d e- vices, a mode fault error occurs. instantly modf will be set as l ogic 1. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software. 3 dismodf mode fault e rror d etection disable this bit is used in combination with the ssoe (spcr.7) bit to determine the fe a- ture of ss pin. dismodf affects only in master mode (mstr = 1). 0 = mode fault detection is not disabled. ss serves as input pin for mode fault detection disregard of ssoe. 1 = mode fault detection is disabled. the feature of ss follows ssoe bit. 2:0 - reserved spdr ? serial peripheral data register 7 6 5 4 3 2 1 0 spdr[7:0] r/w address: f5h reset value: 0000 0000b bit name description 7:0 spdr[7:0] serial p eripheral d ata this byte is used for transmitting or receiving data on spi bus. a write of this byte is a write to the shift register. a read of this byte is actually a read of the read d a- ta buffer. in master mode, a write to this register initiates transmission and rece p- tion of a byte simul taneously. 13.4 operating modes 13.4.1 master m ode the spi can operate in master mode while mstr (spcr.4) is set as 1. only one m aster spi device can initiate transmi s- sion s . a transmission always begins by master through writing to spdr. the byte written to spdr begin s shifting out on N79E845/844/8432 data s heet april 23 201 4 page 77 of 183 revision a2. 6 mosi pin under the control of spclk. simultaneously, another byte shifts in from the slave on the miso pin. after 8 - bit data transfer complete, spif (spsr.7) will automatically set via hardware to indicate one byte data transfer comp lete. at the same time, the data received from the slave is also transferred in spdr. the user can clear spif and read data out of spdr. 13.4.2 slave mode when mstr is 0, the spi operates in slave mode. t he spclk pin becomes input and it will be clock ed by anoth er m a s- ter spi device. the ss pin be be comes input. the master device cannot exchange data with the slave device until the ss pin of the slave device is externally pulled low. before data transmissions occurs, the ss of the slave device should be pulled and remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. if the ss is force to high at the middle of transmissi on, the transmission will be aborted and the rest bits of the receiving shifter buffer will be high and goes into idle state. in slave mode, d ata flows from the m aster to the s lave on mosi pin and flows from the s lave to the m aster on miso pin. the data enters the shift register under the control of the spclk from the master device. after one byte is received in the shift register, it is immediately moved into the read data buffer and the spif bit is set. a read of the spdr is actually a read of the read data buffer. to prevent an overrun and the loss of the byte that caused by the overrun, the slave should read spdr out and the first spif should be cleared before a second transfer of data from the master device comes in the read data buffer . 13.5 cloc k formats and data transfer to accommodate a wide variety of synchronous serial peripherals, the spi has a clock polarity bit cpol (spcr.3) and a clock phase bit cpha (spcr.2). figure 13? 4 spi clock format shows that cpol and cpha compose four different clock formats. the cpol bit denotes the spclk line level in isp idle state. the cpha bit defines the edge on which the mosi and miso lines are sampled. the cpol and cpha should be identical for the master and slave devices on the same system. c ommunicat ing in different data formats with one another will result in undetermined result s . N79E845/844/8432 data s heet april 23 201 4 page 78 of 183 revision a2. 6 cpha = 0 cpha = 1 sample cpol = 0 cpol = 1 clock phase (cpha) clock polarity (cpoh) sample sample sample figure 13? 4 spi clock format in spi, a master device always initiates the transfer. if spi is selected as master mode (mstr = 1) and enabled (spien = 1), writing to the spi data register (spdr) by the master device starts the spi clock and data transfer. after shifting one byte out and receiving one byte in, the spi clock stops and spif (spsr.7) in both master and slave are set. if spi inte r- rupt enable bit espi (eie.6) is set 1 and global interrupt is enabled (ea = 1), the interrupt serv ice routine (isr) of spi will be executed. concerning the slave mode, the ss signal needs to be taken care. as shown in figure 13? 4 spi clock format , when cpha = 0, the first spclk edge is the sampling strobe of msb (for an example of lsbfe = 0, msb first). therefore, the slave should shift its msb data before the first spclk edge. the fa lling edge of ss is used for preparing the msb on miso line. the ss pin therefore should toggle high and then low between each successive serial byte. furthermore, if the slave writes data to the spi data register (s pdr) while ss is low, a write collision error occurs. when cpha = 1, the sampling edge thus locates on the second edge of spclk clock. the slave uses the first spclk clock to shift msb out rather than the ss falling edge. therefore, the ss line can remain low between successive tran s- fers. this format may be preferred in systems having single fixed master and single fixed slave. the ss line of the unique slave device can be tied to v ss as long as only cpha = 1 clock mode is used. note: the spi should be configured before it is enabled (spien = 1) , or a change of lsbfe, mstr, cpol, cpha and spr[1:0] will abort a transmission in progress and force the spi system into idle state. prior to any configuration bit changed, spien should be disabled first. N79E845/844/8432 data s heet april 23 201 4 page 79 of 183 revision a2. 6 spclk cycles spclk (cpol=0) mosi ss output of master [2 ] spif (master) 1 2 3 4 5 6 7 8 spclk (cpol=1) transfer progress [1 ] (internal signal) msb miso 6 5 4 3 2 1 lsb msb input to slave ss lsb 6 5 4 3 2 1 spif (slave) [1] transfer progress starts by a writing spdr of master mcu. [2] ss automatic output affects when mstr = dismodf = ssoe = 1. spclk cycles figure 13? 5 spi clock and data format with c ph a = 0 N79E845/844/8432 data s heet april 23 201 4 page 80 of 183 revision a2. 6 transfer progress [1 ] (internal signal) spclk cycles spclk (cpol=0) mosi ss output of master [2 ] spif (master) 1 2 3 4 5 6 7 8 spclk (cpol=1) msb miso 6 5 4 3 2 1 lsb msb input to slave ss lsb 6 5 4 3 2 1 spif (slave) [1] transfer progress starts by a writing spdr of master mcu. [2] ss automatic output affects when dismodf = ssoe = mstr = 1. [3] if ss of slave is low, the miso will be the lsb of previous data. otherwise, miso will be high. [4] while ss stays low, the lsb will last its state. once ss is released to high, miso will switch to high level. [3 ] [4 ] spclk cycles figure 13? 6 spi clock and data format with c ph a = 1 13.6 slave select pin configuration the N79E845/844/8432 spi provides a flexible ss pin feature for different system requirements. when the spi operates as a slave, ss pin always rules as slave select input. when the master mode is enabled, ss has three different fun c- tions according to dismodf (sps r.3) and ssoe (spcr.7). by default, dismodf is 0. it means that the mode fault detection activate s . ss is configured as a input pin to check if the mode fault appears. on the contrary, if dismodf is 1, mode fault is inactivated and the ssoe bit takes over to control the function of the ss pin. while ssoe is 1, it means the slave select signal will generate automatically to select a slave device. the ss as output pin of the master usually connect s with the ss input pin of the s lave device. the ss output automatically goes low for each transmission when selecting external slave device and goes high during each idl e state to de - select the slave device. while sso e is 0 and dismodf is 1, ss is no more used by the spi and reverts to be a general purpose i/o pin. 13.7 mode fault detection the mode fault detection is useful in a system where more than one spi devices might become masters at the same tim e. it may induce data contention . a mode fault error occurs once the ss is pulled low by others. it indicates that some ot h- N79E845/844/8432 data s heet april 23 201 4 page 81 of 183 revision a2. 6 er spi device is trying to address this master as if it is a slave. instantly t he mstr and spien control bits in the spcr are cleared via hardware to disable spi , mode fault flag modf (spsr.4) is set and an interrupt is generated if espi ( eie .6 ) and ea are enabled. 13.8 write collision error the spi is signal buffered in the transfer dir ec tion and double buffered in the receiving direction. new data for transmi s- sion cannot be written to the shift register until the previous transaction is complete. write collision occurs while an a t- tempt was made to write data to the spdr while a transfer was in progress. spdr is not double buffered in the transmit direction. any writing to spdr cause data to be written directly into the spi shift register . once a write collision error is generated , wcol (spsr.6) will be set as 1 via hardware to indicate a write collision . in this case, t he current transferring data continues its transmission. however the new data that caused the collision will be lost . although the spi logic can detect write collisions in both master and slave modes, a write collision is normally a slave error because a slave has no indicator when a master initiates a transfer. during the receive of slave, a write to spdat causes a write collision under slave mode. wcol flag needs to be cleared via software. 13.9 overrun error for receiving data, the spi is double buffered in the receiving direction. t he received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte . however, the received data should be read from spdr before the n ext data has been completely shifted in. as long as the first byte is read out of the read data buffer and spif is cleared before the next byte is ready to be transferred, no overrun error condition occurs. otherwise t he overrun error o c- curs. in this condi tion, the s econd byte data will not be successfully received into the read data register and the previous data will remains. if overrun occur, spiovf (spsr.5) will be set via hardware . this will also require an interrupt if en a- bled. figure 13 ? 7 spi overrun waveform shows the relationship between the data receiving and the overrun error. shifting data[n] in shifting data[n+1] in spif data[n] data[n] read data buffer shift register shifting data[n+2] in spiovf data[n+2] data[n] receiving begins data[n+1] receiving begins data[n+2] receiveing begins [1 ] when data[n] is received, the spif will be set. [2 ] if spif is not clear before data[n+1] progress done, the spiovf will be set. data[n] will be kept in read data buffer but data [n+1] will be lost. [3 ] spif and spiovf must be cleared by software. [4 ] when data[n+2] is received, the spif will be set again. [1 ] [2 ] [3 ] [3 ] [4 ] figure 13? 7 spi overrun waveform N79E845/844/8432 data s heet april 23 201 4 page 82 of 183 revision a2. 6 13.10 spi i nterrupt s three spi status flags , spif, modf, and spiovf, can generate a n spi event interrupt requests. all of them locate in spsr. spif will be set after completion of data tra nsfer with external device or a new data have been received and copied to spdr. modf becomes set to indicate a low level on ss causing the mode fault state. spiovf denotes a receiving overrun error. if spi interrupt mask is enable d via setting espi ( eie . 6 ) and ea is 1 , cpu will executes the spi interrupt service routine once any of the three flags is set. the user needs to check flags to determine what event caused the inte r- rupt , which th e flags are software clear ed . spif dismodf mstr espi (eie.6) spi interrupt request spiovf mode fault detection ss modf ea figure 13? 8 spi i nterrupt r equest N79E845/844/8432 data s heet april 23 201 4 page 83 of 183 revision a2. 6 org 0000h ljmp start org 004bh ljmp spi_isr org 0100h spi_isr: anl spsr,#7fh reti start: anl spcr,#0dfh ;msb first anl spcr,#0f7h ;the spi clock is low in idle mode orl spcr,#04h ;the data is sample on the second edge of spi clock orl spcr,#10h ;spi in master mode anl spcr,#0fch ;spi clock = fosc/16 setb espi ;enable spi interrupt setb ea orl spcr,#40h ;enable spi function mov spdr,#90h ;send 0x90 to slave orl pcon,#01h ;enter idle mode sjmp $ end N79E845/844/8432 data s heet april 23 201 4 page 84 of 183 revision a2. 6 14 keyboard interrupt (kbi) the N79E845/844/8432 provides the 8 keyboard interrupt function to detect keypad status which key is acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of the N79E845/844/8432 , as shown in the following figure. thi s interrupt may be used to wake up the cpu from idle or power - down mode , after chip is in power - d own or idle m ode. keyboard function is supported through by port 0. it can allow any or all pins of port 0 to be enabled to cause this inte r- rupt. port pins ar e enabled by the setting of bits of kbi0 ~ kbi7 in the kbi register, as shown in the following figure. the keyboard interrupt flag, kbif[7:0] in the kbif(eah), is set when any enabled pin is triggered while the kbi interrupt function is active, an interrup t will be generated if it has been enabled. the kbif[7:0] bit is set by hardware and should be cleared by software. to determine which key was pressed, the kbi will allow the interrupt service routine to poll port 0. kbi supports four triggered conditions low level, falling edge, rising edge and either rising or falling edge detection. the triggered condition of each port pin is individually controlled by two bits kbls1(ech).x and kbls0(ebh).x where x is 0 to 7. after trigger occur s and two machines pass , kbif assert. kbi is generally used to detect an edge transient from peripheral devices like keyboard or keypad. during idle state, the system prefers to enter power - down mode to minimize power consumption and waits for event trigger. the N79E845/844/8432 support s kbi inte rrupt waking up mcu from power d own. note that if kbi is selected as any of edge trigger mode, restrictions should be followed to make power d own woken up valid. for a falling edge waking up, pin state should be high at th e moment of entering power - down mode . respectively, pin state should be low for a rising edge wa k- ing up. N79E845/844/8432 data s heet april 23 201 4 page 85 of 183 revision a2. 6 kbi .0 kbi .5 eie .ekb kbi i nterrupt request p 0.5 p 0.0 kbi . 6 kbi . 7 p 0. x p 0.6 p 0.3 kbi .2 kbi .3 p 0.2 kbi . 4 p 0.4 kbi .1 p 0.1 [ 00] [ 01] [ 11] [ kbis 1 . x, kbis 0 . x] or low - level [ 10] p 0.7 low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect kbi low - leve / edge detect selection x = 0 ~ 7 kbi f .7 kbi f .6 kbi f .5 kbi f .4 kbi f .3 kbi f .2 kbi f .1 kbi f .0 figure 14-1 keyboard interrupt detect ion N79E845/844/8432 data s heet april 23 201 4 page 86 of 183 revision a2. 6 table 14? 1 configuration for different kbi level select ion kbl s1.n kbl s0.n kbi channel n type 0 0 falling edge 0 1 rising edge 1 0 either falling or rising edge 1 1 low level kbi e ? key b oard interrupt enable register 7 6 5 4 3 2 1 0 kbi e .7 kbi e .6 kbi e .5 kbi e .4 kbi e .3 kbi e .3 kbi e .1 kbi e .0 r/w r/w r/w r/w r/w r/w r/w r/w address: e9h reset value: 0000 0000b bit name description 7:0 kbi e key b oard interrupt enable p0[7:0] as a cause of a keyboard interrupt. kbif ? keyboard interface flags 7 6 5 4 3 2 1 0 kbif[7:0] r (level) r/w (edge) address: eah reset value: 0000 0000 b bit name description 7:0 kbifn keyboard i nterface c hannel n f lag if any edge trigger mode of kbi is selected, this flag will be set by hardware if kbi channel n (p0.n) detects a type defined edge. this flag should be cleared by sof t- ware. if the low level trigger mode of kbi is selected, this flag follows the inverse of the input signal?s logic level on kbi channel n (p0.n)l. software cannot control it. kbls0 ? keyboard level select 0 [1] 7 6 5 4 3 2 1 0 kbls0[7:0] r/w address: ebh reset value: 0000 0000 b bit name description 7:0 kbls0[7:0] keyboard l evel s elect 0 N79E845/844/8432 data s heet april 23 201 4 page 87 of 183 revision a2. 6 kbls1 ? keyboard level select 1 [1] 7 6 5 4 3 2 1 0 kbls1[7:0] r/w address: ech reset value: 0000 0000 b bit name description 7:0 kbls1[7:0] keyboard l evel s elect 1 [1] kbls1 and kbls0 is used in combination to determine the input type of each channel of kbi (on p0). refer to table 14 ? 1 configuration for different kbi level select . N79E845/844/8432 data s heet april 23 201 4 page 88 of 183 revision a2. 6 15 analog -to - digital converter (adc) the adc contains a dac which converts the contents of a successive approximation register to a voltage (v dac ) which is compared to the analog input voltage (vin). the output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. a conversion is initiated by setting adcs in the adccon 0 register. adcs can be set by software only or by either hardware or software. note that when the adc function is disabled, all adc related sfr bits will be unavailable and will not effect any other cpu functions. the power of adc block is approached to zero. the software on ly start mode is selected when control bit adccon 0 .5 (adcex) =0. a conversion is then started by setting control bit adccon 0 .3 (adcs) the hardware or software start mode is selected when adccon 0 .5 (adcex) =1, and a conversion may be started by setting adc con 0 .3 as above or by applying a rising edge to external pin stadc. when a conversion is started by applying a rising edge, a low level should be applied to stadc for at least one machine - cycle followed by a high level for at least one machine - cycle. the low - to - high transition of stadc is recognized at the end of a machine - cycle, and the conversion commences at the beginning of the next cycle. when a conversion is initiated by software, the conversion starts at the beginning of the m a- chine - cycle which foll ows the instruction that sets adcs. adcs is actually implemented with tpw flip - flops: a command flip - flop which is affected by set operations, and a status flag which is accessed during read operations. the next two machine - cycles are used to initiate the converter. at the end of the first cycle, the adcs status flag is set end a value of ?1? will be returned if the adcs flag is read while the conversion is in progress. sampling of the analog input commences at the end of the second cycle. during the next eight machine - cycles, the voltage at the p reviously selected pin of port 0 is sampled, and this input vol t- age should be stable to obtain a useful sample. in any event, the input voltage slew rate should be less than 10v/ms to prevent an undefined result. the successive approximation control logic first sets the most significant bit and clears all other bits in the successive a p- proximation register (10 0000 0000b). the output of the dac (50% full scale) is compared to the input voltage vin. if the input v oltage is greater than v dac , the bit remains set; otherwise if is cleared. the successive approximation control logic now sets the next most significant bit (11 0000 0000b or 01 0000 0000b, d e- pending on the previous result), and the v dac is compared to vin again. if the input voltage is greater than v dac , the bit remains set; otherwise it is cleared. this process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approxima tion register. the conversion takes four machine - cycles per bit. N79E845/844/8432 data s heet april 23 201 4 page 89 of 183 revision a2. 6 the end of the 10 - bit conversion is flagged by control bit adccon 0 .4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held i n adccon 0 .7 (adc.1) and adccon 0 .6 (adc.0). the user may ignore the two least significant bits in adccon 0 and use the adc as an 8 - bit converter (8 upper bits in adch). in any event, the total actual conversion time is 35 machine - cycles. adc will be set and the adcs status flag will be reset 35 cycles after the adcs is set. control bits adccon 0 .0 ~ adccon 0 .2 are used to control an analog multiplexer which selects one of 8 analog cha n- nels. an adc conversion in progress is unaffected by an external or software adc start. the result of a completed co n- version remains unaffected provided adci = logic 1; a new adc conversion already in progress is aborted when entering i dle or power - down mode . the result of a completed conversi on (adci = logic 1) remains unaffected when entering i dle mode. when adc c on 0 .5 (adcex) is set by external pin to start adc conversion, after the N79E845/844/8432 entry idle mode, p1.4 can start adc conversion at least one machine - cycle. dac msb lsb successive approximation register vin + - comparator start ready (stop) successive approximation control logic v dac figure 15-1 successive approximation adc the adc circuit has its own supply pins (av dd and avss) and one pins (vref+) connected to each end of the dac?s resistance - ladder that the av dd and vref+ are connected to v dd and avss is connected to v ss . the ladder has 1023 equally spaced taps, separated by a resistance of ?r?. the first tap is located 0.5r above a v ss , and the last tap is located 0.5r below vref+. this gives a total ladder res istance of 1024r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error. for input voltages between a v ss and [(vref+) + ? lsb], the 10 - bit result of an a/d conversion will be 0000000000b = 000h. for input voltag es between [(vref+) ? 3/2 lsb] and vref+, the result of a conversion will be 1111111111b = 3ffh. avref+ and av ss may be between av dd + 0.2v and av ss ? 0.2 v. avref+ should be positive with respect to av ss , and the input voltage (vin) should be between avre f+ and av ss. the result can always be calculated according to the following formula: result = avref vin 1024 + or result = vdd vin 1024 N79E845/844/8432 data s heet april 23 201 4 page 90 of 183 revision a2. 6 10-bits adc block adc.[9:0] adci [3] (adccon0.4) adcs [1] (adccon0.3) v dd vref+ v ss aadr[2:0] adccon0[2:0] analog input multiplexer 0 1 p1.4 adcex (adccon0.5) adcclk adc conversion block adcen (adccon1.7) adc1(p0.2) adc2(p0.3) adc3(p0.4) avss avdd [1]. write to adcs to start adc convertion [2]. read from adcs to monitor adc convertion finished or not. note: adcs [2] 0 1 f sys /4 rcclk(adccon1.1) rc22mhz/4 or rc11mhz/2 cpu clk rc osc adc4(p0.5) adc5(p0.6) adc6(p0.7) adc0(p0.1) 0 1 band-gap(1.3v) [3]. read from adci to monitor adc convertion finished or not. adc0sel(adccon1.0) figure 15-2 adc block diagram N79E845/844/8432 data s heet april 23 201 4 page 91 of 183 revision a2. 6 adccon 0 ? adc control register 0 7 6 5 4 3 2 1 0 adc.1 adc.0 adcex adci adcs aadr2 aadr1 aadr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f8h reset value: 0000 0000b bit name description 7 adc.1 adc conversion result. 6 adc.0 adc conversion result. 5 adcex 0 = disable external start of conversion by p1.4. 1 = enable external start of conversion by p1.4. the stadc signal at least 1 machine - cycle. 4 adci 0 = the adc is not busy. 1 = the adc conversion result is ready to be read. an interrupt is invoked if it is en a- bled. it can not set by software. 3 adcs adc start and status: set this bit to start an a/d conversion. it may be also set by stadc if adcex is 1. this signal remains high while the adc is busy and is reset right after adci is set. notes: it is recommended to clear adci before adcs is set. however, if adci is cleared and adcs is set at the same time, a new a/d conversion may start on the same channel. software clearing of adcs will abort conversion in progress. adc cannot start a new conversion while adcs or adci is high. 2 aadr2 adc input select. 1 aadr1 adc input select. 0 aadr0 adc input select. adci adcs adc s tatus 0 0 adc not busy; a conversion can be started. 0 1 adc busy; start of a new conversion is blocked 1 0 conversion completed; the s tart of a new conversion requires adci = 0 1 1 conversion completed; the s tart of a new conversion requires adci = 0 if adc is cleared by software while adcs is set at the same time, a new a/d conversion with the same channel number may be started. however, it is recommended to reset adci before adcs is set. addr2, aadr1, aadr0: adc analog input channel select bits: these bits can only be changed when adci and adcs are both zero. aadr2 aadr1 aadr0 selected analog channel 0 0 0 adc0 (p0.1) 0 0 1 adc1 (p0.2) 0 1 0 adc2 (p0.3) N79E845/844/8432 data s heet april 23 201 4 page 92 of 183 revision a2. 6 0 1 1 adc3 (p0.4) 1 0 0 adc4 (p0.5) 1 0 1 adc5 (p0.6) 1 1 0 adc6 (p 0.7 ) adch ? adc converter result register 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 r/w r/w r/w r/w r/w r/w r/w r/w address: e2 h reset value: 0000 0000b bit name description 7:0 adc h adc conversion result bits [9:2] . adccon 1 ? adc control register 7 6 5 4 3 2 1 0 adcen - - - - - rcclk adc0sel r/w - - - - - r/w r/w address: e1 h reset value: 0000 0000b bit name description 7 adcen 0 = disable adc circuit. 1 = enable adc circuit. 6:2 - reserved 1 rcclk 0 = the f sys /4 clock is used as adc clock. 1 = the internal rc/2 clock is used as adc clock. 0 adc0sel 0 = select adc channel 0 as input. 1 = select band - gap (~1.3v) as input. p0dids ? port0 digital input disable 7 6 5 4 3 2 1 0 p0dids[7:0] r/w r/w r/w r/w r/w r/w r/w r/w address: f6h reset value: 0000 0000b bit name description 7:0 p0dids.x 1 = disable digital function for each port0. 0 = enable digital function for each port0. N79E845/844/8432 data s heet april 23 201 4 page 93 of 183 revision a2. 6 the demo code of adc channel 0 with clock source = fsys/4 is as follows : org 0000h ljmp start org 005bh ;adc interrupt service routine clr adci ;clear adc flag reti start: orl p0dids,#02h ; disable digital function for p0.1 orl p0m1,#02h ; adc0(p0.1) is input-only mode anl p0m2,#0fdh anl adccon0,#0f8h ;adc0(p0.1) as adc channel anl adccon1,#0fdh ;the fsys/4 clock is used as adc clock. setb eadc ;enable adc interrupt setb ea orl adccon1,#80h ;enable adc function convert_loop: setb adcs ;trigger adc orl pcon,#01h ;enter idle mode mov p0,adch ;converted data put in p0 and p1 mov p1,adcl sjmp convert_loop end N79E845/844/8432 data s heet april 23 201 4 page 94 of 183 revision a2. 6 16 inter - integrated circuit (i 2 c) 16.1 features the inter - integrated circuit (i 2 c) bus serves as a serial interface between the microcontroller and the i 2 c devices such as eeprom, lcd module, and so on. the i 2 c bus used two wires design (a serial data line sda and a serial clock line scl) to transfer information between devices. the i 2 c bus uses bidirectional data transfer between masters and slaves. there is no central master and the multi - master system is allowed by arbitration between simultaneously transmitting masters. the serial clock synchronization allows devices with different bit rates to communicate via one serial bus. the i 2 c bus supports four transfer modes including master transmitter mode, master receiver mode, slave receiver mode, and slave transmitter mode. the i 2 c interface only supports 7 - bit addressing mode and general call can be accepted. the i 2 c can meet both standard (up to 100kbps) and fast (up to 400kbps) speeds. 16.2 functional description for the bidirectional transfer operation, the sda and scl pins should be connected to open - drain pads. this implements a wired - and function which is esse ntial to the operation of the interface. a low level on a i 2 c bus line is generated when one or more i 2 c devices output a ?0?. a high level is generated when all i 2 c devices output ?1?, allowing the pull - up r e- sistors to pull the line high. in t he N79E845/8 44/8432 , the user should set output latches of p 1.2 and p 1.3 . as logic 1 before enabling the i 2 c function by setting i2cen (i2con.6). the p 1.2 and p 1.3 are configured as the open - drain i/o once the i 2 c function is enabled. the p 1 m2 and p 1 m1 will be also re - configured. the schmitt trigger input buffer is strongly recommended to be enabled by setting p1s for improved glitch suppression. sda scl n79e84x sda scl slave device sda scl other mcu sda scl vdd r up r up figure 16? 1 i 2 c b us interconnection N79E845/844/8432 data s heet april 23 201 4 page 95 of 183 revision a2. 6 the i 2 c is considered free when both lines are high. meanwhile, any device which can operate as a master can occupy the bus and generate one transfer after generating a start condition. the bus now is considered busy before the transfer ends by sending a stop con dition. the master generates all of the serial clock pulses and the start and stop cond i- tion. however if there is no start condition on the bus, all devices serve as not addressed slave. the hardware looks for its own slave address or a general call addres s. (the general call address detection may be enabled or disabled by gc (i2addr.0).) if the matched address is received, an interrupt is requested. every transaction on the i 2 c bus is 9 bits long, consisting of 8 data bits (msb first) and a single acknowl edge bit. the number of bytes per transfer (defined as the time between a valid start and stop condition) is unrestricted but each byte has to be followed by an acknowledge bit. the master device generates 8 clock pulse to send the 8 - bit data. after the 8 th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the 9 th clock pulse. after 9 th clock pulse, the data receiving device can hold scl line stretched low if next receiving is not prepared ready. it forces the next byte transaction suspended. the data transaction continues when the receiver releases the scl line. sda scl msb lsb ack 1 2 8 9 start condition stop condition figure 16? 2 i 2 c bus protocol 16.2.1 start and stop condition s the protocol of the i 2 c bus defines two states to begin and end a transfer, start (s) and stop (p) conditions. a start condition is defined as a high - to - low transition on the sda line while scl line is high. t he stop condition is define d as a low - to - high transition on the sda line while scl line is high. a start or a stop condition is always ge n- erated by the master and i 2 c bus is considered busy after a start condition and free after a stop condition. after iss u- ing the stop condition suc cessful, the original master device will release the control authority and turn back as a not a d- dressed slave. consequently, the original addressed slave will become a not addressed slave. the i 2 c bus is free and li s- tens to next start condition of next tra nsfer. a data transfer is always terminated by a stop condition generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start (sr) condition and address the pervious or another slave wit h- out first ge nerating a stop condition. various combinations of read/write formats are then possible within such a transfer. N79E845/844/8432 data s heet april 23 201 4 page 96 of 183 revision a2. 6 sda scl start stop start repeated start stop figure 16? 3 start, repeated start, and stop conditions 16.2.2 7- bit addre ss with data format following the start condition is generated, one byte of special data should be transmitted by the master. it includes a 7 - bit long slave address (sla) following by an 8 th bit, which is a data direction bit (r/w), to address the target slave device and determine the direction of data flow. if r/w bit is 0, it indicates that the master will write information to a selected slave, and if this bit is 1, it indicates that the ma ster will read information from the slave. an address packet consisting of a slave address and a read (r) or a write (w) bit is called sla+r or sla+w, respectively. a transmission basically co n- sists of a start condition, a sla+r/w, one or more data packets and a stop condition. after the specified slave is addressed by sla+r/w, the second and following 8 - bit data bytes issue by the master or the slave devices according to the r/w bit configuration. there is an exception called ?general call? address which c an address all devices by giving the first byte of data all 0. a general call is used when a master wishes to transmit the same message to several slaves in the system. when this a d- dress is used, other devices may respond with an acknowledge or ignore it a ccording to individual software configuration. if a device response the general call, it operates as like in the slave - receiver mode. N79E845/844/8432 data s heet april 23 201 4 page 97 of 183 revision a2. 6 sda scl 1-7 8 9 8 9 1-7 1-7 8 9 address w/r ack s p data ack data ack figure 16? 4 data format of an i 2 c transfer during the data transaction period, the data on the sda line should be stable during the high period of the clock, and the data line can only change when scl is low. 16.2.3 acknowledge the 9 th scl pulse for any transferred byte is dedicated as an acknowledge (ac k). it allows receiving devices (which can be the master or slave) to respond back to the transmitter (which can be also the master or slave) by pulling the sda line low. the acknowledge - related clock pulse is generated by the master. the transmitter shoul d release control of sda line during the acknowledge clock pulse. the ack is an active - low signal, pulling the sda line low during the clock pulse high duty, indicates to the transmitter that the device has received the transmitted data. commonly, a receiv er which has been addressed is requested to generate an ack after each byte has been received. when a slave receiver does not acknowledge (nack) the slave address, the sda line should be left high by the slave so that the mater can generate a stop or a rep eated start condition. if a slave - receiver does acknowledge the slave address, it switches itself to not addressed slave mode and cannot receive any more data bytes. this slave leaves the sda line high. the master should generate a stop or a repeated start co n- dition. if a master - receiver is involved in a transfer, because the master controls the number of bytes in the transfer, it should si g- nal the end of data to the slave - transmitter by not generating an acknowledge on the last byte. the slave - transmitter then switches to not addressed mode and release the sda line to allow the master to generate a stop or a repeated start condition. N79E845/844/8432 data s heet april 23 201 4 page 98 of 183 revision a2. 6 sda output by transmitter scl from master 1 2 8 9 start condition sda output by receiver sda = 0, acknowledge (ack ) sda = 1 , not acknowledge (nack) clock pulse for acknowledge bit figure 16? 5 acknowledge bit 16.2.4 arbitration a master may start a transfer only if the bus is free. it is possible for two or more masters to generate a start condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the compe ting master devices to place a '1' (high) on sda while another master transmits a '0' (low) switches off its data output stage because the level on the bus does not match its own level. the arbitration lost master switches to the not a d- dressed slave immedi ately to detect its own slave address in the same serial transfer whether it is being addressed by the winning master. it also releases sda line to high level for not affecting the data transfer initiated by the winning master. however, the arbitration los t master continues scl line to generate the clock pulses until the end of the byte in which it loses the arbitration. if the address matches the losing master?s own slave address, it switches to the addressed - slave mode. arbitration is carried out by all m asters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda valu e while another master outputs a low value. arbitration will continue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will continue into the data packet. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits or acknowledge bit. N79E845/844/8432 data s heet april 23 201 4 page 99 of 183 revision a2. 6 data 1 from master 1 start condition master 1 loses arbitration for data 1 sda it immediately switches to not addressed slave and outputs high level data 2 from master 2 sda line scl line figure 16? 6 arbitration procedure of two masters since the control of i 2 c bus is decided solely by the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bu s. slaves are not involved in the arbitration procedure. 16.3 control registers of i 2 c there are five control registers to interface the i 2 c bus. they are i2con, i2sta , i2dat, i2addr, i2clk, and i2tmr , which registers provide protocol control, status, data transmit and receive functions, clock rate configuration, and timeout notification. the following registers relate to i 2 c function. i2con ? i 2 c control 7 6 5 4 3 2 1 0 - i2cen sta sto si aa - - - r/w r/w r/w r/w r/w - - address: c0h reset value: 0000 0000b bit name description 7 - reserved 6 i2cen i 2 c b us e nable 0 = i 2 c bus is disabled. 1 = i 2 c bus is enabled. before enabling the i 2 c, px.x and px.x port latches should be set to logic 1. once the i 2 c bus is enabled , sda pin (px.x) and scl pin (px.x) will be automatically switched to the open - drain mode. pxm2 and pxm1 registers will be also re - configured accor d- ingly. N79E845/844/8432 data s heet april 23 201 4 page 100 of 183 revision a2. 6 bit name description 5 sta start f lag when sta is set, the i 2 c generates a start condition if the bus is free. if the bus is busy, the i 2 c waits for a stop condition and generates a start condition fo l- lowing. if sta is set while the i 2 c is already in master mode and one or more bytes have been transmitted or received , the i 2 c generates a repeated start condition. note that sta can be set anytime even in a slave mode, but sta is not hardware automat i- cally cleared after start or repeated start condition has been detected. the user should take care of it by clearing sta manually. 4 sto stop f lag when sto is set if the i 2 c is in master mode , a stop condition is transmitted to the bus. sto is automatically cleared by hardware once the stop condition has been detected on the bus. the sto flag setting is also used to recover the i 2 c device from the bus error state (i2sta as 00h). in this case, no stop condition is transmitted to the i 2 c bus. if the sta and sto bits are both set and the device is original in master mode , the i 2 c bus will generate a stop condition and immediate ly follow a start condition. if the device is in slave mode, sta and sto simultaneous setting should be avoid from issuing illegal i 2 c frames. 3 si serial i nterrupt f lag the si flag is set by hardware when one of 25 possible i 2 c status (besides f8h st a- tus) is entered. after si is set, the software should read i2sta register to determine which step has been passed and take actions for next step. si is cleared by software. before the si is cleared, the low period of scl line is stretched. the transaction is suspended. it is useful for the slave device to deal with previous data bytes until ready for receiving the next byte. the serial transaction is suspended until si is cleared by software. after si is cleared, i 2 c bus will continue to generate start or r epeated start condition, stop condition, 8 - bit data, or so on depending on the software configuration of controlling byte or bits. therefore the user should take care of it by preparing suitable setting of registers before si is software cleared. 2 aa ack nowledge a ssert f lag if the aa flag is set, an ack (low level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver which can be a master, an addressed slave, an own - address - matching slave, or a genera - call accept a- ble slave. if the aa flag is cleared, a nack (high level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver which can be a master, an addressed slave. a device with its own aa flag cleared will ignore its own salve address and the general call. consequently, si will note be asserted and no interrupt is requested. note that if an addressed slave does not return an ack under slave receiver mode or not receive an ack under slave transmi tter mode, the slave device will become a not addressed slave. it cannot receive any data until its aa flag is set and a master addresses it again. there is a special case of i2sta value c8h occurs under slave transmitter mode. before the slave device tran smit the last data byte to the master, aa flag can be cleared as 0. then after the last data byte transmitted, the slave device will actively switch to not addressed slave mode of disconnecting with the master. the further reading of the master will be all ffh. 1:0 - reserved N79E845/844/8432 data s heet april 23 201 4 page 101 of 183 revision a2. 6 i2sta ? i 2 c status 7 6 5 4 3 2 1 0 i2sta [7:3 ] 0 0 0 r r r r address: bdh reset value: 1111 1000b bit name description 7:3 i2sta[7:3] i 2 c s tatus c ode the most five bits of i2sta contains the status code. there are 26 possible st a- tus codes. when i2sta is f8h, no relevant state information is available and si flag keeps 0. all other 25 status codes correspond to the i 2 c states. when each of the status is entered, si will be set as logic 1 and a interrupt is requested. 2:0 - reserved the least three bits of i2sta are always read as 0. i2dat ? i 2 c data 7 6 5 4 3 2 1 0 i2dat[7:0] r/w address: bch reset value: 0000 0000b bit name description 7:0 i2dat[ 7 :0] i 2 c d ata i2dat contains a byte of the i 2 c data to be transmitted or a byte which has just r e- ceived. data in i2dat remains as long as si is logic 1. the result of reading or writing i2dat during i 2 c transceiving progress is unpredicted. while data in i2dat is shifted out, data on the bus is simult aneously being shifted in to update i2dat. i2dat always shows the last byte that presented on the i 2 c bus. thus the event of lost arbitration, the original value of i2dat changes after the tran s- action. i2addr ? i 2 c own slave address 7 6 5 4 3 2 1 0 i2 addr[7:1] gc r/w r/w address: c 1 h reset value: 0000 0000b bit name description 7:1 i2addr[7:1] i 2 c device?s own s lave a ddress in m aster mode: these bits have no effect. in s lave mode: the 7 bits define the slave address of this i 2 c device by the user . the master should address this i 2 c device by sending the same address in the first byte data after a start or a repeated start condition. if the aa flag is set, this i 2 c device will acknowledge the master after receiving its own address and become an add ressed slave. otherwise, the a d- dressing from the master will be ignored. N79E845/844/8432 data s heet april 23 201 4 page 102 of 183 revision a2. 6 bit name description 0 gc general call b it in m aster mode: this bit has no effect. in s lave mode: 0 = general call is always ignored . 1 = general call is recognized if aa flag is 1; otherwise, it is ignored if aa is 0. i2clk ? i 2 c clock 7 6 5 4 3 2 1 0 i2clk[7:0] r/w address: be h reset value: 0000 1110b bit name description 7:0 i2clk[7:0] i 2 c c lock s etting in master mode : this register determines the clock rate of i 2 c bus when the device is in master mode . the clock rate follows the formula below. clk 2 i 1 f f pheri c i 2 + = the default value will make the clock rate of i 2 c bus 400kbps if the clock system 24 mhz with divm 1/4 mode is used. note that the i2clk value of 00h and 01h are not valid. this is an implement lim i- tation. in s lave mode: this byte has no effect. in slave mode, the i 2 c device will automatically synchronize with any given clock rate up to 400kps. 16.4 operation modes in i 2 c protocol definition, there are four operating modes including master transmitter, master receiver, slave receive, and slave transmitter. there is also a special mode called general call. its operat ion is similar to master transmitter mode. 16.4.1 master transmit ter mode in m aster t ransmitter mode, several bytes of data are transmitted to a slave receiver. the master should prepare by setting desired clock rate in i2clk and enabling i 2 c bus by writing i2cen (i2con.6) as logic 1. the master transmitter mode may now be entered by setting sta (i2con.5) bit as 1. the hardware will test the bus and generate a start condition as soon as the bus becomes free. after a start condition is successfully produced, the si flag (i2con.3) will be set and the status code in i2sta s how 08h. the progress is continued by loading i2dat with the target slave address and the data direction bit ?write? (sla+w). the si bit should then be cleared to commence sla+w transaction. N79E845/844/8432 data s heet april 23 201 4 page 103 of 183 revision a2. 6 after the sla+w byte has been transmitted and an acknowledge (ack ) has been returned by the addressed slave device, the si flag is set again and i2sta is read as 18h. the appropriate action to be taken follows the user defined communic a- tion protocol by sending data continuously. after all data is transmitted, the master can send a stop condition by setting sto (i2con.4) and then clearing si to terminate the transmission. a repeated start condition can be also generated without sending stop condition to immediately initial another transmission. 08h a start has been transmitted (sta,sto,si,aa) = (x,0, 0,x) i2dat = sla+w sla+w will be transmitted (sta,sto,si,aa) = (1,0,0,x) a start will be transmitted 18h sla+w has been transmitted ack has been received or 20h sla+w has been transmitted nack has been received (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted (sta,sto,si,aa)=(0,0,0,x) i2dat = data byte data byte will be transmitted (sta,sto,si,aa)=( 0,1,0,x) a stop will be transmitted a stop has been transmitted (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted a stop has been transmitted 28h data byte has been transmitted ack has been received or 30h data byte has been transmitted nack has been received 10h a repeated start has been transmitted (sta,sto,si,aa) =(0,0,0,x) i2dat = sla+r sla+r will be transmitted 38h arbitration lost in sla+w or data byte to master receiver 68h or 78h arbitration lost and addressed as slave receiver ack has been transmitted or b0 h arbitration lost and addressed as slave transmitter ack has been transmitted (sta,sto,si,aa)=(0,0,0,x) not addressed slave will be entered (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free (sta,sto, si,aa) = (x,0,0,1) i2dat = sla+w sla+w will be transmitted mr mt to corresponding slave mode figure 16? 7 flow and status of master transmitter mode 16.4.2 master receiver mode in the master receiver mode, several bytes of data are received from a slave transmitter. the transaction is initialized just as the master transmitter mode. following the start condition, i2dat should be loaded with the target slave address N79E845/844/8432 data s heet april 23 201 4 page 104 of 183 revision a2. 6 and the data d irection bit ?read? (sla+r). after the sla+r byte is transmitted and an acknowledge bit has been r e- turned, the si flag is set again and i2sta is read as 40h. si flag then should be cleared to receive data from the slave transmitter. if aa flag (i2con.3) is set, the master receiver will acknowledge the slave transmitter. if aa is cleared, the master receiver will not acknowledge the slave and release the slave transmitter as a not addressed slave. after that, the master can generate a stop condition or a rep eated start condition to terminate the transmission or initial another one. 08h a start has been transmitted (sta,sto,si,aa ) = (x,0 ,0,x) i2dat = sla+r sla+r will be transmitted (sta,sto ,si,aa) = ( 1,0,0,x) a start will be transmitted 40h sla+r has been transmitted ack has been received or 48h sla+r has been transmitted nack has been received (sta,sto, si,aa)=(1,0,0,x) a repeated start will be transmitted (sta,sto,si,aa)=(0,0,0,1) data byte will be received ack will be transmitted (sta,sto, si,aa)=(0,1,0,x) a stop will be transmitted a stop has been transmitted (sta,sto, si,aa)=(1,1, 0,x) a stop followed by a start will be transmitted a stop has been transmitted 50h data byte has been received ack has been transmitted i2dat = data byte 10h a repeated start has been transmitted (sta,sto,si,aa) =(0,0, 0,x) i2dat = sla+w sla+w will be transmitted 38h arbitration lost in sla+w or nack bit to master transmitter (sta,sto,si,aa)=(0,0,0, x) not addressed slave will be entered (sta,sto,si,aa)=(1,0,0,x ) a start will be transmitted when the bus becomes free (sta,sto,si,aa )=(0,0, 0,0) data byte will be received nack will be transmitted 58h data byte has been received nack has been transmitted i2dat = data byte 68h or 78h arbitration lost and addressed as slave receiver ack has been transmitted or b0 h arbitration lost and addressed as slave transmitter ack has been transmitted (sta, sto,si, aa) = (x,0 ,0,1) i2dat = sla+ r sla+r will be transmitted mr mt to corresponding slave mode figure 16? 8 flow and status of master receiver mode 16.4.3 slave receiver mode in s lave r eceiver mode, severa l bytes of data are received form a master transmitter. before a transmission is co m- menced, i2addr should be loaded with the address to which the device will respond when addressed by a master. i2clk does not affect in slave mode. the aa bit should be set to enable acknowledging its own slave address or general call. N79E845/844/8432 data s heet april 23 201 4 page 105 of 183 revision a2. 6 after the initialization above, the i 2 c wait until it is addressed by its own address with the data direction bit ?write? (sla+w) or by general call addressing. the slave receiver mode may also be entered if arbitration is lost. after the slave is addressed by sla+w, it should clear its si flag to receive the data from the master transmitter. if the aa bit is 0 during a transaction, the slave will return a non - acknowledge after the next received data byte. the slave will be be come not addressed and isolate with the master. it cannot receive any byte of data with i2dat remaining the prev i- ous byte of data which is just received. (sta,sto,si,aa) = (0,0,0, 1) if own sla+w is received, ack will be transmitted 60h own sla+w has been received ack has been transmitted i2dat = own sla+w or 68h arbitration lost and own sla+w has been received ack has been transmitted i2dat = own sla+w (sta,sto,si,aa)=( x,0,0,0) data byte will be received nack will be transmitted (sta,sto,si,aa)=(0,0,0,0) not addressed slave will be entered; no recognition of own sla or general call (sta,sto,si,aa)=(0,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1 88h data byte has been received nack has been transmitted i2dat = data byte a0 h a stop or repeated start has been received (sta,sto,si,aa)=(x,0,0,1) data byte will be received ack will be transmitted 80h data byte has been received ack has been transmitted i2dat = data byte (sta,sto,si,aa)=(1,0,0,0) not addressed slave will be entered; no recognition of own sla or general call; a start will be transmitted when the bus becomes free (sta,sto,si,aa)=(1,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1; a start will be transmitted when the bus becomes free figure 16? 9 flow and status of slave receiver mode 16.4.4 slave transmitter mode in s lave t ransmitter mode, several bytes of data are transmitted to a master receiver. after i2addr and i2con values are given, the i 2 c wait until it is addressed by its own address with the data direction bit ?read? (sla+r). the slave transmitter mode may also be entered if arbitration is lost. N79E845/844/8432 data s heet april 23 201 4 page 106 of 183 revision a2. 6 after the slave is addressed by sla+w, it should clear its si flag to transmit the data to the master transmitter. normally the master receiver will return an acknowledge after every byte of data is transmitted by the slave. if the acknowledge is not received, it will transmit all ?1? data if it continues the transaction. it becomes a not addressed slave. if the aa fla g is cleared during a transaction, the slave transmit the last byte of data. the next transmitting data will be all ?1? and the sl ave becomes not addressed. (sta,sto,si,aa) = (0,0,0,1) if own sla+r is received, ack will be transmitted a8 h own sla+r has been received ack has been transmitted i2dat = own sla+r or b0 h arbitration lost and own sla+r has been received ack has been transmitted i2dat = own sla+r (sta,sto,si,aa)=(x,0,0,x) i2dat = data byte data byte will be transmitted nack will be received (sta,sto,si,aa)=(0,0,0,0) not addressed slave will be entered; no recognition of own sla or general call (sta,sto,si,aa)=(0,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1 c 0 h data byte has been transmitted nack has been received a0 h a stop or repeated start has been received (sta,sto,si,aa)=(x,0,0,1) i2dat = data byte data byte will be transmitted ack will be received b8 h data byte has been transmitted ack has been received (sta,sto,si,aa)=(1,0,0,0) not addressed slave will be entered; no recognition of own sla or general call; a start will be transmitted when the bus becomes free (sta,sto,si,aa)=(1,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1; a start will be transmitted when the bus becomes free (sta,sto,si,aa)=(x,0,0,0) i2dat = last data byte data byte will be transmitted ack will be received c 8 h last data byte has been transmitted ack has been received figure 16? 10 flow and status of slave transmitter mode 16.4.5 general call the general call is a special condition of slave receiver mode by sending all ?0? data in slave address with data direction bit. the slave addressed by a general call has different status codes in i2sta with normal slave receiver mode. the ge n- eral call may be also produced if arbitration is lost. N79E845/844/8432 data s heet april 23 201 4 page 107 of 183 revision a2. 6 (sta,sto,si,aa) = (0,0,0,1) if general call is received, ack will be transmitted 70h general call has been received ack has been transmitted i2dat = 00 h or 78h arbitration lost and general call has been received ack has been transmitted i2dat = 00 h (sta,sto, si,aa)=( x,0,0,0) data byte will be received nack will be transmitted (sta,sto,si,aa)=(0,0,0,0) not addressed slave will be entered; no recognition of own sla or general call (sta,sto,si,aa )=(0,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1 98h data byte has been received nack has been transmitted i2dat = data byte a0 h a stop or repeated start has been received (sta,sto,si,aa)=(x,0,0,1) data byte will be received ack will be transmitted 90h data byte has been received ack has been transmitted i2dat = data byte (sta,sto,si,aa)=( 1,0,0,0) not addressed slave will be entered; no recognition of own sla or general call; a start will be transmitted when the bus becomes free (sta,sto,si,aa)=( 1,0,0,1) not addressed slave will be entered; own sla will be recognized; general call will be recognized if gc = 1; a start will be transmitted when the bus becomes free figure 16? 11 . flow and status of general call mode 16.4.6 miscellaneous states there are two i2sta status codes that do not correspond to the 24 defined states, which are mentioned in previous se c- tions , which are f8h and 00h states. the first status code f8h indicates that no relevant information is available during each transaction. meanwhile , the si flag is 0 and no i 2 c interrupt is required. the other status code 00h means a bus error has occurred during a transaction. a bus error is caused by a start or stop condition appearing temporarily at an illegal position such as the second through e ighth bits in an address byte or a data byte including the acknowledge bit. when a bus error occurs, the si flag is set immediately. when a bus error is d e- tected on the i 2 c bus, the operating device immediately switches to the not addressed salve mode, rel ease sda and scl lines, sets the si flag, and loads i2sta 00h. to recover from a bus error, the sto bit should be set as logic 1 and si N79E845/844/8432 data s heet april 23 201 4 page 108 of 183 revision a2. 6 should be cleared. after that, sto is cleared by hardware and release the i 2 c bus without issuing a real stop condition waveform. there is a special case if a start or a repeated start condition is not successfully generated for i 2 c bus is obstructed by a low level on sda line e.g. a slave device out of bit synchronization, the problem can be solved by transmitting add i- tional clock pulses on the scl line. the i 2 c hardware transmits additional clock pulses when the sta bit is set, but no start condition can be generated because the sda line is pulled low. when the sda line is eventually released, a no r- mal start condition is transmitted, state 08h is entered, and the serial transaction continues. if a repeated start co n- dition is transmitted while sda is obstructed low, the i 2 c hardware also performs the same action as above. in this case, state 08h is entered instead of 10h after a successful start condition is transmitted. note that the software is not i n- volved in solving these bus problems. 16.5 typical structure of i 2 c interrupt service routine the following software example in c language for keil c51 compiler shows the typical structure of the i 2 c interrupt service routine including the 26 state service routines and may be used as a base for user applications. user can follow or modify it for their own application. if one or more of the five modes are not used, the assoc iated state service routines may be removed, but care should be taken that a deleted routine can never be invoked. void i2c_isr (void) interrupt 6 { switch (i2sta) { //=============================================== //bus error, always put in isr for noise handling //=============================================== case 0x00: /*00h, bus error occurs*/ sto = 1; //recover from bus error break; //=========== //master mode //=========== case 0x08: /*08h, a start transmitted*/ sta = 0; //sta bit should be cleared by software i2dat = sla_addr1; //load sla+w/r break; case 0x10: /*10h, a repeated start transmitted*/ sta = 0; i2dat = sla_addr2; break; //======================= //master transmitter mode //======================= case 0x18: /*18h, sla+w transmitted, ack received*/ i2dat = next_send_data1; //load data break; case 0x20: /*20h, sla+w transmitted, nack received*/ sto = 1; //transmit stop aa = 1; //ready for ack own sla+w/r N79E845/844/8432 data s heet april 23 201 4 page 109 of 183 revision a2. 6 break; case 0x28: /*28h, data transmitted, ack received*/ if (conti_tx_data) //if continuing to send data i2dat = next_send_data2; else //if no data to be sent { sto = 1; aa = 1; } break; case 0x30: /*30h, data transmitted, nack received*/ sto = 1; aa = 1; break; //=========== //master mode //=========== case 0x38: /*38h, arbitration lost*/ sta = 1; //retry to transmit start if bus free break; //==================== //master receiver mode //==================== case 0x40: /*40h, sla+r transmitted, ack received*/ aa = 1; //ack next received data break; case 0x48: /*48h, sla+r transmitted, nack received*/ sto = 1; aa = 1; break; case 0x50: /*50h, data received, ack transmitted*/ data_received1 = i2dat; //store received data if (to_rx_last_data1) //if last data will be received aa = 0; //not ack next received data else //if continuing receiving data aa = 1; break; case 0x58: /*58h, data received, nack transmitted*/ data_received_last1 = i2dat; sto = 1; aa = 1; break; //==================================== //slave receiver and general call mode //==================================== case 0x60: /*60h, own sla+w received, ack returned*/ aa = 1; break; case 0x68: /*68h, arbitration lost in sla+w/r own sla+w received, ack returned */ aa = 0; //not ack next received data after //arbitration lost sta = 1; //retry to transmit start if bus free break; case 0x70: //70h, general call received, ack returned aa = 1; break; case 0x78: /*78h, arbitration lost in sla+w/r general call received, ack returned*/ aa = 0; sta = 1; break; N79E845/844/8432 data s heet april 23 201 4 page 110 of 183 revision a2. 6 case 0x80: /*80h, previous own sla+w, data received, ack returned*/ data_received2 = i2dat; if (to_rx_last_data2) aa = 0; else aa = 1; break; case 0x88: /*88h, previous own sla+w, data received, nack returned, not addressed slave mode entered*/ data_received_last2 = i2dat; aa = 1; //wait for ack next master addressing break; case 0x90: /*90h, previous general call, data received, ack returned*/ data_received3 = i2dat; if (to_rx_last_data3) aa = 0; else aa = 1; break; case 0x98: /*98h, previous general call, data received, nack returned, not addressed slave mode entered*/ data_received_last3 = i2dat; aa = 1; break; //========== //slave mode //========== case 0xa0: /*a0h, stop or repeated start received while still addressed slave mode*/ aa = 1; break; //====================== //slave transmitter mode //====================== case 0xa8: /*a8h, own sla+r received, ack returned*/ i2dat = next_send_data3; aa = 1; //when aa is ?1?, not last data to be //transmitted break; case 0xb0: /*b0h, arbitration lost in sla+w/r own sla+r received, ack returned */ i2dat = dummy_data; aa = 0; //when aa is ?0?, last data to be //transmitted sta = 1; //retry to transmit start if bus free break; case 0xb8: /*b8h, previous own sla+r, data transmitted, ack received*/ i2dat = next_send_data4; if (to_tx_last_data) //if last data will be transmitted aa = 0; else aa = 1; break; case 0xc0: /*c0h, previous own sla+r, data transmitted, nack received, not addressed slave mode entered*/ aa = 1; N79E845/844/8432 data s heet april 23 201 4 page 111 of 183 revision a2. 6 break; case 0xc8: /*c8h, previous own sla+r, last data trans- mitted, ack received, not addressed slave mode entered*/ aa = 1; break; }//end of switch (i2sta) si = 0; //si should be the last step of i2c isr while(sto); //wait for stop transmitted or bus error //free, sto is cleared by hardware }//end of i2c_isr 16.6 i 2 c time - out there is 1 4 - bit time - out counter which can be used to deal with the i 2 c bus hang - up. if the time - out counter is enabled, the counter starts up counting until it overflows. meanwhile tif will be set by hardware and requests i 2 c interrupt. when time - out counter is enabled, setting flag si to high will reset counter and restart counting up after si is cleared. if the i 2 c bus hangs up, it causes the si flag not set for a period. the 14 - bit time - out counter will overflow and require the interrupt service. 1 0 f sys 1/4 14-bit i 2 c time-out counter i2tf clear counter i2tmren div i2cen si figure 16? 12 i 2 c time - out count i2toc ? i 2 c time - out counter 7 6 5 4 3 2 1 0 - - - - - i2tocen div i2t o f - - - - - r/w r/w r/w address: bf h reset value: 0000 0000b bit name description 7:3 - reserved 2 i2tocen i 2 c t ime - out c ounter e nable 0 = the i 2 c time - out counter is disabled. 1 = the i 2 c time - out counter is enabled. N79E845/844/8432 data s heet april 23 201 4 page 112 of 183 revision a2. 6 bit name description 1 div i 2 c time - out c ounter c lock d ivider 0 = the divider of i 2 c time - out counter is 1/1 of f sys . 1 = the divider of i 2 c time - out counter is 1/4 of f sys . 0 i2tof i 2 c ti me- out c ounter o verflow f lag i2tof flag is set by hardware if 14 - bit i 2 c time - out counter overflows. i2tof flag is cleared by software. 16.7 i 2 c interrupts there are two i 2 c flags, si and i2t o f. both of them can generate an i 2 c event interrupt requests. if i 2 c interrupt mask is enabled via setting ei2c (eie. 0 ) and ea is 1, cpu will executes the i 2 c interrupt service routine once any of the two flags is set. the user needs to check flags to determine what event caused the interrupt. both of i 2 c flags are cleared by software. N79E845/844/8432 data s heet april 23 201 4 page 113 of 183 revision a2. 6 17 pulse width modulated (pwm) 17.1 features pwm (pulse width modulation) signal is a useful control solution in wide application field. it can used on motor driving, fan control, backlight brightness tuning, led light dimming, or simulating as a simple digital to analog converter output through a lo w pass filter circuit. the N79E845/844/8432 provides four channels, maximum 10 - bit pwm output. 17.2 functional description the N79E845/844/8432 contain s four pulse width modulated (pwm) channels which generate pulses of programmable length and interval. the out put for pwm0 is on p0.1, pwm1 on p1.6, pwm2 on p1.7 and pwm3 on p0.0. after chip reset the internal output of the each pwm channel is a ?1?. in this case before the pin will reflect the state of the interna l pwm output a ?1? should be written to each port bit that serves as a pwm output. a block diagram is shown in figure 17- 1 . the interval between successive outputs is controlled by 1 0 ? bit down counter which uses configurable internal clock pre - scalar as its input. the pwm counter clock has the frequency as the clock source f pwm = f sys / pre - scalar . when the counter reaches underflow it is reloaded with a user selectable value. this mechanism allows the user to set the pwm frequency at any integer sub ? multiple of the microcontroller clock frequency. the repetition frequency of the pwm is given by: pwm frequency = pwmp + 1 f pwm , pwm active level duty = pwmp + 1 pwmn . where pwmp is contained in pwmph and pwmpl as described in the following. pwmpl ? pwm counter low bits register 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 r/w r/w r/w r/w r/w r/w r/w r/w address: d9h reset value: 0000 0000b bit name description 7:0 pwmp l pwm counter bits register bit[7:0]. pwmph ? pwm counter high bits register 7 6 5 4 3 2 1 0 - - - - - - pwmp. 9 pwmp. 8 - - - - - - r/w r/w address: d1h reset value: 0000 0000b bit name description 7:2 - reserved N79E845/844/8432 data s heet april 23 201 4 page 114 of 183 revision a2. 6 bit name description 1:0 pwmp h pwm counter bits register bit[9:8]. the user should follow the initialization steps below to start generating the pwm signal output. in the first step by setting clrpwm (pwmcon0.4), it ensures the 10 - bit down counter a determined value. after setting all period and duty regi s- ters, pwmrun (pwmcon0.7) can be set as logic 1 to trigger the 10 - bit down counter running. in the beginni ng the pwm output remains high until the counter value is less than the value in duty control registers of pwmnh and pwmnl . at this point the pwm output goes low until the next underflow. when the 10 - bit down counter underflows, pwmp buf f- er register will b e reloaded in 10 - bit down counter. it continues pwm signal output by repeating this routine. the hardware for all period and duty control registers is double buffered designed. therefore the pwmp and pwmn re g- isters can be written to at any time, but the pe riod and duty cycle of pwm will not updated immediately until the l oad (pwmcon0.6) is set and previous period is complete. this allows updating the pwm period and duty glitch less oper a- tion. pwm0l ? pwm 0 low register 7 6 5 4 3 2 1 0 pwm 0 .7 pwm 0 .6 pwm 0 .5 pwm 0 .4 pwm 0 .3 pwm 0 .2 pwm 0 .1 pwm 0 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: dah reset value: 0000 0000b bit name description 7:0 pwm0 l pwm 0 low bits register bit[7:0]. pwm0h ? pwm 0 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 0 . 9 pwm 0 . 8 - - - - - - r/w r/w address: d2h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm0 h pwm 0 high bits register bit[9:8]. pwm1l ? pwm 1 low register 7 6 5 4 3 2 1 0 pwm 1 .7 pwm 1 .6 pwm 1 .5 pwm 1 .4 pwm 1 .3 pwm 1 .2 pwm 1 .1 pwm 1 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: dbh reset value: 0000 0000b bit name description 7:0 pwm1l pwm 0 low bits register bit[7:0]. N79E845/844/8432 data s heet april 23 201 4 page 115 of 183 revision a2. 6 pwm1h ? pwm 1 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 1 . 9 pwm 1 . 8 - - - - - - r/w r/w address: d3h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm1h pwm 1 high bits register bit[9:8]. pwm2l ? pwm 2 low register 7 6 5 4 3 2 1 0 pwm 2 .7 pwm 2 .6 pwm 2 .5 pwm 2 .4 pwm 2 .3 pwm 2 .2 pwm 2 .1 pwm 2 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: ddh reset value: 0000 0000b bit name description 7:0 pwm2l pwm 2 low bits register bit[7:0]. pwm2h ? pwm 2 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 2 . 9 pwm 2 . 8 - - - - - - r/w r/w address: d5h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm2h pwm 2 high bits register bit[9:8]. pwm3l ? pwm 3 low register 7 6 5 4 3 2 1 0 pwm 3 .7 pwm 3 .6 pwm 3 .5 pwm 3 .4 pwm 3 .3 pwm 3 .2 pwm 3 .1 pwm 3 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: deh reset value: 0000 0000b bit name description 7:0 pwm3l pwm 0 low bits register bit[7:0]. pwm3h ? pwm 3 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 3 . 9 pwm 3 . 8 - - - - - - r/w r/w address: d6h reset value: 0000 0000b bit name description 7:2 - reserved N79E845/844/8432 data s heet april 23 201 4 page 116 of 183 revision a2. 6 bit name description 1:0 pwm3h pwm 3 high bits register bit[9:8]. N79E845/844/8432 data s heet april 23 201 4 page 117 of 183 revision a2. 6 figure 17-1 pwm block diagram N79E845/844/8432 data s heet april 23 201 4 page 118 of 183 revision a2. 6 a compare value greater than the counter reloaded value is in the pwm output being permanently low. in addition there are two special cases. a compare value of all zeroes, 000h, causes the output to remain permanently high. a compare value of all ones, 3ffh, results in the pwm output remaining permanently low. again the compare value is loaded into a compare register. the transfer from this holding register to the actual compare r egister is under program control. the register assignments are shown below where the number immediately following ?pwmn? identifies the pwm output. therefore, the pwm0 controls the width of pwm0, pwm1 the width of pwm1 etc. the overall functioning of the pwm module is controlled by the contents of the pwmcon0 register. the operation of most of the control bits is straightforward. for example, there is an invert bit for each output which causes results in the output to have the opposite value compared to it s non - inverted output. the transfer of the data from the counter and compare registers to the control registers is controlled by the pwmcon0.6 (load) while pwmcon0.7 (pwmrun) allows the pwm to be either in the run or idle state. the user can monitor when u nderflow causes the transfer to occur by monitoring the transfer bit pwcon1.6 (load) or pwmcon0.5 (cf flag). note that cf does not assert interrupt. when the transfer takes place the pwm logic automatically resets those bits by the next clock cycle. a load ing of new period and duty by setting load should be ensured complete by monitoring it and waiting for a hardware automatic clearing load bit. any updating of pwm control registers during load bit as logic 1 will cause unpredictable output. pwmcon0 ? pwm c ontrol register 0 7 6 5 4 3 2 1 0 pwmrun load cf clrpwm pwm3i pwm2i pwm1i pwm0i r/w r/w r/w r/w r/w r/w r/w r/w address: dch reset value: 0000 0000b bit name description 7 pwmrun 0 = pwm is not running. 1 = pwm counter is running. 6 load 0 = the registers value of pwmp and comparators are never loaded to counter and co m- parator registers. 1 = the pwmp register will be load value to counter register after counter underflow, and hardware will clear by next clock cycle. 5 cf 10- bit counter overflow flag: 0 = 10 - bit counter down count is not underflow. 1 = 10 - bit counter down count is underflow. 4 clrpwm 1 = clear 10 - bit pwm counter to 000h. 3 pwm3i 0 = pwm3 output is non - inverted. 1 = pwm3 output is inverted. 2 pwm2i 0 = pwm2 output is non - inverted. 1 = pwm2 output is inverted. N79E845/844/8432 data s heet april 23 201 4 page 119 of 183 revision a2. 6 bit name description 1 pwm1i 0 = pwm1 output is non - inverted. 1 = pwm1 output is inverted. 0 pwm0i 0 = pwm0 output is non - inverted. 1 = pwm0 output is inverted. the fact that the transfer from the counter and pwmn register to the working registers(10 - bit counter and compare regi s- ter) only occurs when there is an underflow in the counter results in the need for the user?s program to observe the follo w- ing precautions. if pwmcon0 is written with load set without run be ing enabled the transfer will never take place. thus if a subsequent write sets run without load the compare and counter values will not be those expected. if load and run are set, and prior to underflow there is a subsequent load of pwmcon0 which sets run but not load, the load will never take place. again the compare and counter values that existed prior to the update attempt will be used. as outlined above the load bit can be polled to determine when the load occurs. unless there is a compelling reason t o do otherwise, it is recommended that both pwmrun (pwmcon0.7), and load (pwmcon0.6) be set when pwmcon0 is written. when the pwmrun bit, pwmcon0.7 is cleared the pwm outputs take on the state they had just prior to the bit being cleared. in general , this state is not known. to place the outputs in a known state when pwmrun is cleared the compare registers can be written to either the ?always 1? or ?always 0? so the output will have the output desired when the counter is halted. after this pwmcon0 should be written with the load and run bits are enabled. after this is done pwmcon0 to polled to find that the load or cf flag has taken place. once the load has occurred the run bit in pwmcon0 can be cleared. the outputs will retain the state they had just prior to the run being cleared. if the brake pin (see discussion b e- low in section concerning the operation of pwmcon1) is not used to control the brake function, the ?brake when not running? function can be used to cause the outputs to have a given state when th e pwm is halted. this approach should be used only in time critical situations when there is not sufficient time to use the approach outlined above since going from the brake state to run without causing an undefined state on the outputs is not straightfor ward. a discussion on this topic is included in the pwmcon1 section . pwmcon1 ? pwm control register 1 7 6 5 4 3 2 1 0 bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b r/w r/w r/w r/w r/w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 7 bkch see the following table ( when bken is set ) . 6 bkps 0 = brake is asserted if p0.2 is low. 1 = brake is asserted if p0.2 is high 5 bpen see the following table ( when bken is set ) . N79E845/844/8432 data s heet april 23 201 4 page 120 of 183 revision a2. 6 bit name description 4 bken 0 = brake is never asserted. 1 = brake is enabled, and see the following table . 3 pwm3b 0 = pwm3 output is low, when brake is asserted. 1 = pwm3 output is high, when brake is asserted. 2 pwm2b 0 = pwm2 output is low, when brake is asserted. 1 = pwm2 output is high, when brake is asserted. 1 pwm1b 0 = pwm1 output is low, when brake is asserted. 1 = pwm1 output is high, when brake is asserted. 0 pwm0b 0 = pwm0 output is low, when brake is asserted. 1 = pwm0 output is high, when brake is asserted. brake condition t able bpen bkch break condition 0 0 brake on (software brake and keeping brake) 0 1 on, when pwm is not running (pwmrun=0), the pwm output condition is follow pwmnb setting. off, when pwm is running (pwmrun=1). 1 0 brake on, when break pin asserted, no pwm output, the bit of pwmrun will be cleared and bkf flag will be set. t he pwm output condition is follow pwmnb setting. 1 1 no active. pwmcon2 ? pwm control register 2 7 6 5 4 3 2 1 0 - - - - fp1 fp0 - bkf - - - - r/w r/w - r/w address: d7h reset value: 0000 0000b bit name description 7:4 - reserved 3:2 fp[1:0] select pwm frequency pre - scalar select bits. the clock source of pre - scalar, fpwm is in phase with f sys if pwmrun=1. fp[1:0] fpwm 00 f sys (default) 01 f sys /2 10 f sys /4 11 f sys /16 1 - reserved N79E845/844/8432 data s heet april 23 201 4 page 121 of 183 revision a2. 6 bit name description 0 bkf e xternal b rake p in f lag 0 = pwm is not brake. 1 = pwm is brake by external brake pin. it will be cleared by software. the brake function, which is controlled by the contents of the pwmcon1 register, is somewhat unique. in general when brake is asserted the four pwm outputs are forced to a user selected state, namely the state selected by pwmcon1 bits 0 to 3. as shown in the description of the operation of the pwmc on1 register if pwmcon1.4 is a ?1? brake is asserted under the control pwmcon1.7, bkch, and pwmcon1.5, bpen. as shown if both are a ?0? brake is asserted. if pwmcon1.7 is a ?1? brake is asserted when the run bit, pwmcon0.7, is a ?0.? if pwmcon1.6 is a ?1? brake is a s- serted when the brake pin, p0.2, has the same polarity as pwmcon1.6. when brake is asserted in response to this pin the run bit, pwmcon0.7, is automatically cleared and bkf(pwmcon2.0) flag will be set. the combination of both pwmcon1.7 and pwmco n1.5 being a ?1? is not allowed. since the brake pin being asserted will automatically clear the run bit of pwmcon0.7and bkf(pwmcon2.0) flag will be set, the user program can poll this bit or enable pwm?s brake interrupt to determine when the brake pin ca uses a brake to occur. the other method for detecting a brake caused by the brake pin would be to tie the brake pin to one of the e x- ternal interrupt pins. this latter approach is needed if the brake signal can be of insufficient length to ensure that it ca n be captured by a polling routine. when, after being asserted, the condition causing the brake is removed, the pwm outputs go to whatever state that had immediately prior to the brake. this means that to go from brake being asserted to having the pwm run without going through an indeterminate state care should be taken. if the brake pin causes brake to be asserted the following prototype code will allow the pwm to go from brake to run smoothly by software polling bkf flag or en a- ble pwm?s interrupt. note th at if a narrow pulse on the brake pin causes brake to be asserted, it may not be possible to go through the above code before the end of the pulse. in this case, in addition to the code shown, an external latch on the brake pin may be required to ensure th at there is a smooth transition in going from brake to run. N79E845/844/8432 data s heet april 23 201 4 page 122 of 183 revision a2. 6 pwm demo code is as follows : org 0h sjmp start org 100h start: mov pwmph,#0 ;pwm frequency = fsys/(1+pwmp) mov pwmpl,#0ffh ;if fsys=20mhz, pwm frequency=78.1khz mov pwm0h,#0 mov pwm0l,#080h ;pwm0(p0.1) duty = pwm0/(1+pwmp) mov pwm1h,#0 mov pwm1l,#0a0h ;pwm1(p1.6) duty = pwm1/(1+pwmp) mov pwm2h,#0 mov pwm2l,#0c0h ;pwm2(p1.7) duty = pwm2/(1+pwmp) mov pwm3h,#0 mov pwm3l,#0f0h ;pwm3(p0.0) duty = pwm3/(1+pwmp) orl pwmcon0,#0d0h ;start pwm mov pwmcon1,#30h ;pwm will be stopped when p0.2 is low level. ;pwm output condition is follow pwmnb setting. ;in this case, pwm0b=pwm1b=pwm2b=pwm3b=0 end N79E845/844/8432 data s heet april 23 201 4 page 123 of 183 revision a2. 6 18 timed access protection (ta) the N79E845/844/8432 has several features like the watchdog timer, the isp function, boot select control, etc. are cr u- cial to proper operation of the system. if leaving these control registers unprotected, errant code may write undetermined value into t hem, it results in incorrect operation and loss of control. to prevent this risk, the N79E845/844/8432 ha s a protection scheme which limits the write access to critical sfrs. this protection scheme is done using a timed access. the following registers are related to ta process. ta ? timed access 7 6 5 4 3 2 1 0 ta[7:0] w address: c7h reset value: 1111 1111b bit name description 7:0 ta[7:0] timed access the timed access register controls the access to protected sfrs. to access pr o- tected bits, the user should first write aah to the ta and immediately followed by a write of 55h to ta. after the two steps, a writing permission window is opened for three machine - cycles during which the user may write to protected sfrs. in timed access method, the bits, which are protected, have a timed write enable window. a write is successful only if this window is active, otherwise the write will be discarded. when the software writes aah to ta, a counter is started. this counter wait s for three machine - cycles looking for a write of 55h to ta. if the second write of 55h occurs within three machine - cycles of the first write of aah, then the timed access window is opened. it remains open for three machine - cycles during which the user may write to the protected bits. after three machine - cycles, this window automatically clo s- es. once the window closes , the procedure should be repeated to access the other protected bits. not that the ta protected sfrs are required timed access for writing. h owever, the reading is not protected. the user may read ta protected sfr without giving aa h and 55 h to ta. the suggestion code for opening the timed access window is shown below. (clr ea) ;if any interrupt is enabled, disable temporarily mov ta, #0aah mov ta, #55h (instruction that writes a ta protected register) (setb ea) ;resume interrupts enabled the writes of aah and 55h should occur within 3 machine - cycles of each other. interrupts should be disabled during this procedure to avoid delay between these two writes. if the is no interrupt enabled, the clr ea and setb ea instructions can be left out. once the timed access window closes, the procedure should be repeated to access the other protected bits. examples of timed assessing are shown to i llus trate correct or incorrect writing process es . example 1, N79E845/844/8432 data s heet april 23 201 4 page 124 of 183 revision a2. 6 (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine-cycles. mov ta,#55h ;2 machine-cycles. orl chpcon,#data ;2 machine-cycles. (setb ea) ;resume interrupts enabled example 2, (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine-cycles. mov ta,#55h ;2 machine-cycles. nop ;1 machine-cycle. nop ;1 machine-cycle. anl isptrg,#data ;2 machine-cycles. (setb ea) ;resume interrupts enabled example 3 , (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine-cycles. nop ;1 machine-cycle. mov ta,#55h ;2 machine-cycles. mov wdcon0,#data1 ;2 machine-cycles. orl pmcr,#data2 ;2 machine-cycles. (setb ea) ;resume interrupts enabled example 4 , (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine-cycles. nop ;1 machine-cycle. nop ;1 machine-cycle. mov ta,#55h ;2 machine-cycles. anl wdcon0,#data ;2 machine-cycles. (setb ea) ;resume interrupts enabled in the first example , the writing to the pro tected bits is done before the three machine - cycle window closes. in ex ample 2 , however, the writing to isptrg does not complete during the window open ing, there will be no change of the value of isptrg . in example 3 , the wdcon0 is successful written but the pmc r access is out of the three machine - cycle wi n- dow. therefore pmc r value will not change either. in example 4 , the second write 55h to ta completes after three m a- chine - cycles of the first write ta of aah , therefore the timed access window in not opened at all, and the write to the protected bit fails. in the N79E845/844/8432 , the ta protected sfrs inclu de pmcr (a3h) , chpcon (9fh), isptrg (a4 h) , shbda (9ch), wdcon0 ( d8 h) , and wdcon1 ( ab h) . N79E845/844/8432 data s heet april 23 201 4 page 125 of 183 revision a2. 6 19 interrupt system the N79E845/844/8432 has four priority level of interrupts structure with 14 interrupt sources. each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. in addition, the interrupts can be globally en a- bled or disabled. 19.1 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level triggered, depending on bits it0 and it1. the bi ts ie0 and ie1 in the tcon register are the flags which are checked to generate the interrupt. in the edge triggered mode, the intx inputs are sampled in every machine - cycle. if the sample is high in one cycle and low in the next, then a high to low transi tion is detected and the interrupts request flag iex in tcon is set. the flag bit requests the interrupt. since the external interrupts are sampled every machine - cycle, they have to be held high or low for at least one complete machine - cycle. the iex flag is automatically cleared when the service routine is called. if the level triggered mode is s e- lected, then the requesting source has to hold the pin low till the interrupt is serviced. the iex flag will not be cleared b y the hardware on entering the servic e routine. if the interrupt continues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same source. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags , which flags are set by the overflow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. the watchdog timer can be used as a system monitor or a simple timer. in either case, when the timeout count is reached, the watchdog timer interrupt flag wd tr f ( wdcon0 .3) is set. if the interrupt is enabled by the enable bit eie.4, then an interrupt will occur. the serial block can generate interrupt on reception or transmission. there are two inte rrupt sources from the serial block, which are obtained by the ri and ti bits in the scon sfr , which bits are not automatically cleared by the har d- ware, and the user will have to clear these bits using software. i 2 c will generate an interrupt due to a new sio state present in i2sta register, if both ea and es bits (in ie register) are both enabled. spi asserts interrupt flag, spif, upon completion of data transfer with an external device. if spi interrupt is enabled (espi at eie.6), a serial peripheral inte rrupt is generated. spif flag is software clear, by writing 0 . modf and spiovf will also generate interrupt if occur. they share the same vector address as spif. the adc can generate interrupt after finished adc converter. there is one interrupt source, which is obtained by the adci bit in the adccon 0 sfr. this bit is not automatically cleared by the hardware, and the user will have to clear this bit using software. pwm brake interrupt flag bkf is generated if p0.2 (brake pin) detects a high (bkps=1) or low (bkps=0) at port pin. at this moment, bkf ( pwmcon2 .0) is set by hardware and it should be cleared by software. pwm period interrupt flag cf is set by hardware when its? 10 - bit down counter underflow and is only cleared by software. bkf is set the pwm inte r- rupt is requested if pwm interrupt is enabled (epwm=1). N79E845/844/8432 data s heet april 23 201 4 page 126 of 183 revision a2. 6 keyboard interrupt is generated when any of the keypad connected to p0 pins detects a low - level or edge changed at port pin. each keypad interrupt can be individually enabled or disabled. the kbi flag (kbif[7:0]) should be cleared by sof t- ware. por detect can cause pof flag, bof , to be asserted if power voltage drop below bod voltage level. interrupt will occur if ebo d (ie.5) and global interrupt enable (ea) are set. all the bits that generate interrupts can be set or reset by software, and thereby software initiated interrupts can be gene r- ated. each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, in which can be cleared to disable all the interrupts. ie0 ie1 bof kbif[7:0] ekb ebod ex1 ex0 si es ri+ti et1 tf1 et0 tf0 ea interrupt to cpu wakeup (if in power down) epwm espi spif modf spiovf bkf et2 tf2 wdtf eadc adci wdten ecptf cptf0 cptf1 ei2c i2tof figure 19-1 interrupt flag block diagram N79E845/844/8432 data s heet april 23 201 4 page 127 of 183 revision a2. 6 19.2 priority level structure there are four priority levels for the interrupts, highest, high, low and lowest. the interrupt sources can be individually set to either high or low levels. naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. ho w- ever there exists a pre - defined hierarchy amongst the interrup ts themselves. this hierarchy comes into play when the i n- terrupt controller has to resolve simultaneous requests having the same priority level. this hierarchy is defined as shown in table 19- 3 , the interrupts are numbered starting from the highest priority to the lowest. the interrupt flags are sampled every machine - cycle. in the same machine - cycle, the sampled interrupts are polled and their priority i s resolved. if certain conditions are met then the hardware will execute an internally generated lcall i n- struction which will vector the process to the appropriate interrupt vector address. the conditions for generating the lcall include 1. an interrupt of equal or higher priority is not currently being serviced. 2. the current polling cycle is the last machine - cycle of the instruction currently being executed. 3. the current instruction does not involve a write to ie, eie, ip , ip h, eip or iph1 registers an d is not a reti. if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated every m a- chine - cycle, with the interrupts sampled in the same machine - cycle. if an interrupt flag is active in one cycle but not r e- s ponded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts are not remembered; every polling cycle is new. the processor responds to a valid interrupt by executing an lcall i nstruction to the appropriate service routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine. in case of external interrupt, int0 and int1, the flags are cleared only if they are edge triggered. in case of serial interrupts, the flags are not cleared by har d- ware. in the case of timer 2 interrupt, the flags are not cleared by hardware. the hardware lcall behaves exactly like the software lcall instruction. this instruction saves the program counter contents onto the stack, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lca ll , which address of vector for the different sources are as follows N79E845/844/8432 data s heet april 23 201 4 page 128 of 183 revision a2. 6 table 19- 1 vector l ocations for i nterrupt s ources source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h timer 2 overflow/ match 002bh i 2 c interrupt 0033h kbi interrupt 003bh bod interrupt 0043h spi interrupt 004bh watchdog timer 0053h adc interrupt 005bh capture 0063h pwm brake interrupt 0073h the vector table is not evenly spaced; this is to accommodate future expansions to the device family. table 19- 2 four - level i nterrupt p riority priority bits interrupt priority level ipxh ipx 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) execution continues from the vectored address till an reti instruction is executed. on execution of the reti instruction the processor pops the stack and loads the pc with the contents at the top of the stack. the user should watch out for the status of th e stack is restored to whatever after the hardware lcall, if the execution is to return to the interrupted pr o- gram. the processor does not notice anything if the stack contents are modified and will proceed with execution from the address put back into pc. note that a ret instruction would perform exactly the same process as a reti instruction, but it would not inform the interrupt controller that the interrupt service routine is completed, and would leave the controller still thinking that the service rout ine is underway. the N79E845/844/8432 uses a four - priority level interrupt structure. this allows great flexibility in controlling the ha n- dling of the N79E845/844/8432 many interrupt sources. the N79E845/844/8432 supports up to 14 interrupt sources. each i nterrupt source can be individually enabled or disabled by setting or clearing a bit in registers ie or eie. the ie register also contains a global disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programme d to one of four priority levels by setting or clearing bits in the ip , ip h, eip , and eip h registers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but N79E845/844/8432 data s heet april 23 201 4 page 129 of 183 revision a2. 6 not by another interrupt of the same or lower priority. th e highest priority interrupt service cannot be interrupted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve simultaneous r e- quests of the same priority level. the followi ng t able summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ran k ing, and whether each interrupt may wake up the cpu from power - down mode . N79E845/844/8432 data s heet april 23 201 4 page 130 of 183 revision a2. 6 table 19- 3 summar y of interrupt sources description interrupt flag bit(s) vector address interrupt enable bit(s) flag cleared by interrupt priority arbitration ranking power - d own wake - up external interrupt 0 ie0 0003h ex0 (ie0.0) hardware, software ip h.0, ip .0 1 (highest) yes bod detect bof 0043h ebo d (ie.5) software ip h.5, ip .5 2 yes watchdog timer wd t f 0053h ewdi ( e ie.4) software eip h.4, eip .4 3 yes timer 0 interrupt tf0 000bh et0 (ie.1) hardware, software ip h.1, ip .1 4 no i 2 c interrupt si i2tof 0033h ei2 c ( e ie.0) software eip h.0, eip .0 5 no adc converter adci 005bh ead c (ie.6) software ip h.6, ip .6 6 yes (1) external interrupt 1 ie1 0013h ex1 (ie.2) hardware, software ip h.2, ip .2 7 yes kbi interrupt kb i f [7:0] 003bh ekb ( e ie.1) software eip h.1, eip .1 8 yes timer 1 interrupt tf1 001bh et1 (ie.3) hardware, software ip h.3, ip .3 9 no serial port tx and rx ti & ri 0023h es (ie.4) software ip h.4, ip .4 10 no pwm interrupt bkf 0073h epwm (eie.5) software eip h.5, eip .5 11 no spi spif + modf + spiovf 004bh espi (eie.6) software eip h. 6 , eip . 6 12 no timer 2 overflow/match tf2 002b h et2 (eie.7) software eip h. 7 , eip . 7 13 no capture c apf 0 - 1 0063h ecptf (eie. 2 ) software ip h. 7 , ip . 7 14 (lowest) no [1] the adc converter can wake up ? power - down mode ? when its clock source is from internal rc. N79E845/844/8432 data s heet april 23 201 4 page 131 of 183 revision a2. 6 19.3 interrupt response time the response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instru c- tion underway. in the case of external interrupts int0 to ri+ti, they are sampled at c3 of every machine - cycle and then their corresponding interrupt flags iex will be set or reset. the timer 0 and 1 overflow flags are set at c3 of the machine - cycle in which overflow has occurred , which flag value s are polled only in the next machine - cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this lcall itself takes four machine - cycles to be completed. thus there is a minimum time of five machine - c ycles between the interrupt flag being set and the interrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is b e- ing serviced, the interrupt latency tim e is obviously depend ent on the nature of the service routine currently being execu t- ed. if the polling cycle is not the last machine - cycle of the instruction being executed, an additional delay is introduced. the maximum response time (if no other interrup t is in service) occurs if the N79E845/844/8432 perform s a write to ie, eie, ip , ip h, eip or eip h and then executes a mul or div instruction. from the time an interrupt source is activated, the longest reaction time is 12 machine - cycles. this includes 1 ma chine - cycle to detect the interrupt, 3 machine - cycles to complete the ie, eie, ip , ip h, eip or eip h access, 5 machine - cycles to complete the mul or div instruction and 4 m a- chine - cycles to complete the hardware lcall to the interrupt vector location. thus in a single - interrupt system the interrupt response time will always be more than 5 machine - cycles and not more than 12 machine - cycles. the maximum latency of 12 machine - cycle is 48 clock cycles. note that in the standard 8051 the ma x- imum latency is 8 mach ine - cycles which equals 96 machine - cycles. this is a 50% reduction in terms of clock periods. 19.4 sfr of interrupt the sfrs associated with the se interrupts are listed below. N79E845/844/8432 data s heet april 23 201 4 page 132 of 183 revision a2. 6 ie ? interrupt enable (bit - addressable) 7 6 5 4 3 2 1 0 ea eadc ebo d es et1 ex1 et0 ex0 r/w r/w r/w r/w r/w r/w r/w r/w address: a8h reset value: 0000 0000b bit name description 7 ea enable a ll i nterrupt this bit globally enables/disables all interrupts. it overrides the individual interrupt mask settings. 0 = disable all interrupt sources. 1 = enable each interrupt depending on its individual mask setting. individual i n- terrupts will occur if enabled. 6 eadc enable adc i nterrupt 5 ebod enable bod i nterrupt 4 es enable s erial p ort (uart) i nterrupt 0 = disable all uart interrupts. 1 = enable interrupt generated by ti (scon.1) or ri (scon.0). 3 et1 enable timer 1 i nterrupt 0 = disable timer 1 interrupt 1 = enable interrupt generated by tf1 (tcon.7). 2 ex1 enable e xternal interrupt 1 0 = disable external interrupt 1. 1 = enable interrupt generated by 1 int pin (p1.4). 1 et0 enable timer 0 i nterrupt 0 = disable timer 0 interrupt 1 = enable interrupt generated by tf0 (tcon.5). 0 ex0 enable e xternal i nterrupt 0 0 = disable external interrupt 0. 1 = enable interrupt generated by 0 int pin (p1.3). e ie ? extensive interrupt enable 7 6 5 4 3 2 1 0 et2 espi epwm ewdi - ecptf ekb ei2 c N79E845/844/8432 data s heet april 23 201 4 page 133 of 183 revision a2. 6 r/w r/w r/w r/w - r/w r/w r/w address: e8 h reset value: 0000 0000b bit name description 7 et2 0 = disable timer 2 interrupt. 1 = enable timer 2 interrupt. 6 espi spi interrupt enable: 0 = disable spi interrupt. 1 = enable spi interrupt. 5 epwm 0 = disable pwm interrupt when external brake pin was braked. 1 = enable pwm interrupt when external brake pin was braked. 4 ewdi 0 = disable watchdog timer interrupt. 1 = enable watchdog timer interrupt. 3 - reserved 2 ecptf 0 = disable capture interrupts. 1 = enable capture interrupts. 1 ekb 0 = disable keypad interrupt. 1 = enable keypad interrupt. 0 ei2c 0 = disable i 2 c interrupt. 1 = enable i 2 c interrupt. ip ? interrupt priority - 0 register 7 6 5 4 3 2 1 0 pcap padc pbod ps pt1 px1 pt0 px0 r/w r/w r/w r/w r/w r/w r/w r/w address: b8h reset value: 0000 0000b bit name description 7 pcap 1 = set interrupt high priority of capture 0/1/2 as highest priority level. 6 padc 1 = set interrupt priority of adc as higher priority level. 5 pbod 1 = set interrupt priority of bod detector as higher priority level. 4 ps 1 = set interrupt priority of serial port 0 as higher priority level. 3 pt1 1 = set interrupt priority of timer 1 as higher priority level. N79E845/844/8432 data s heet april 23 201 4 page 134 of 183 revision a2. 6 bit name description 2 px1 1 = set interrupt priority of external interrupt 1 as higher priority level. 1 pt0 1 = set interrupt priority of timer 0 as higher priority level. 0 px0 1 = set interrupt priority of external interrupt 0 as higher priority level. iph ? interrupt high priority register 7 6 5 4 3 2 1 0 pcaph padch pbo d h psh pt1h px1h pt0h px0h r/w r/w r/w r/w r/w r/w r/w r/w address: b7h reset value: 0000 0000b bit name description 7 pcaph 1 = set interrupt high priority of capture 0/1/2 as highest priority level. 6 padch 1 = set interrupt high priority of adc as the highest priority level. 5 pbo d h 1 = set interrupt high priority of bod detector as the highest priority level. 4 psh 1 = set interrupt high priority of serial port 0 as the highest priority level. 3 pt1h 1 = ro set interrupt high priority of timer 1 as the highest priority level. 2 px1h 1 = set interrupt high priority of external interrupt 1 as the highest priority level. 1 pt0h 1 = set interrupt high priority of timer 0 as the highest priority level. 0 px0h 1 = set interrupt high priority of external interrupt 0 as the highest priority level. eip ? interrupt priority - 1 register 7 6 5 4 3 2 1 0 pt2 pspi ppwm pwdi - - pkb pi2 r/w r/w r/w r/w - - r/w r/w address: ffh reset value: 0000 0000b bit name description 7 pt2 1 = set interrupt priority of timer 2 as higher priority level. 6 pspi 1 = set interrupt priority of spi as higher priority level. 5 ppwm 1 = set interrupt priority of pwm?s brake as higher priority level. 4 pwdi 1 = set interrupt priority of watchdog as higher priority level. 3:2 - reserved N79E845/844/8432 data s heet april 23 201 4 page 135 of 183 revision a2. 6 bit name description 1 pkb 1 = set interrupt priority of keypad as higher priority level. 0 pi2 1 = set interrupt priority of i 2 c as higher priority level. eiph ? interrupt high priority - 1 register 7 6 5 4 3 2 1 0 pt2h pspih ppwmh pwdih - - pkbh pi2h r/w r/w r/w r/w - - r/w r/w address: f7h reset value: 0000 0000b bit name description 7 pt2h 1 = s et interrupt high priority of timer 2 as the highest priority level. 6 pspih 1 = s et interrupt high priority of spi as the highest priority level. 5 ppwmh 1 = s et interrupt high priority of pwm?s external brake pin as the highest priority level. 4 pwdih 1 = s et interrupt high priority of watchdog as the highest priority level. 3:2 - reserved 1 pkbh 1 = s et interrupt high priority of keypad as the highest priority level. 0 pi2h 1 = set interrupt high priority of i 2 c as the highest priority level. tcon ? timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w address: 88h reset value: 0000 0000b bit name description 3 ie1 external i nterrupt 1 e dge f lag this flag is set via hardware when an edge/level of type defined by it1 is detec t- ed. if it1 = 1, this bit will remain set until it is cleared via software or at the begi n- ning of the external interrupt 1 service routine. if it1 = 0, this flag is the inverse of the 1 int input signal's logic level. N79E845/844/8432 data s heet april 23 201 4 page 136 of 183 revision a2. 6 bit name description 2 it1 external i nterrupt 1 t ype s elect ion this bit selects whether the 1 int pin will detect falling edge or low level triggered interrupts. 0 = 1 int is low level triggered. 1 = 1 int is falling edge triggered. 1 ie0 external i nterrupt 0 e dge f lag this flag is set via hardware when an edge/level of type defined by it0 is detec t- ed. if it0 = 1, this bit will remain set until cleared via software or at the beginning of the external interrupt 0 service routine. if it0 = 0, this flag is the inverse of the 0 int input signal's logic level. 0 it0 external i nterrupt 0 t ype s elect ion this bit selects whether the 0 int pin will detect falling edge or low level triggered interrupts. 0 = 0 int is low level triggered. 1 = 0 int is falling edge triggered. N79E845/844/8432 data s heet april 23 201 4 page 137 of 183 revision a2. 6 20 in system programming ( isp ) the internal program memory and on - chip data flash support both hardware programming and in system programming (isp). hardware programming mode uses gang - writers to reduce programming costs and time to market while the pro d- ucts enter into the mass production state. however , if the product is just under development or the end p roduct needs firmware updating in the hand of an end user , the hardware programming mode will make r epeated programming difficult and inconvenient . isp method makes it easy and possible. the N79E845/844/8432 supports isp mode al lowing a device to be reprogrammed under software control. t he capability to update the application firmware makes v dd = 3.0v ~ 5.5v of applications. isp is performed without removing the microcontroller from the system. the most common method to perform isp is via uart along with the firmware in ldrom. general speaking, pc transfers the new aprom code through serial port. then ld rom firmware receives it and re - programs into aprom through isp commands. nuvoton provides isp fir m- ware, please visit nuvoton 8 - bit microcontroller website below and select ? nuvoton isp - icp programmer?. http://www.nuvoton.com/nuvotonmoss/community/productinfo.aspx?tp_guid=670aaf31 - 5d5c - 45d3- 8a9e - 040e148d55cf 20.1 isp procedure unlike ram?s r e al - time operation, to update flash data often takes long time. furthermore, it is a quite complex timing procedure to erase, program , or read flash data. fortunately, the N79E845/844/8432 carried out the flash operation with convenient mechanism to help t he user update the flash content. after isp enabled by setting ispen (chpcon.0 with ta protect ed ), t he user can easily fill the 16- bit target address in ispah and ispal , data in ispfd and command in ispcn. then the isp is ready to begin by setting a trigge ring bit ispgo (isptrg.0). note that isptrg is also ta pr o- tected. at this moment, the cpu holds the program counter and the built - in isp automation takes over to control the i n- ternal charge - pump for high voltage and the detail signal timing. after isp action completed , the program counter conti n- ues to run the following instructions . the ispgo bit will be automatically cleared. the user may repeat steps above for next isp action if necessary. through this progress, the user can easily e rase, program, and verify the embedded flash by just watching out for the pure software. the following registers are relate d to isp processing. N79E845/844/8432 data s heet april 23 201 4 page 138 of 183 revision a2. 6 chpcon ? chip control ( ta p rotected ) 7 6 5 4 3 2 1 0 swrst ispf lduen - - - bs ispen w r r/w - - - r/w r/w address: 9fh reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 6 ispf isp f ault f lag (read only) the hardware will set this bit when any of the following condition is met: 1. the accessing area is illegal, such as, (a) erasing or programming aprom itself when aprom code runs. (b) erasing or programming ldrom when aprom code runs but lduen is 0. (c) erasing, programming, or reading config bytes when aprom code runs . (d) erasing or programming ldrom itself when ldrom code runs . (e) accessing oversize. 2. the isp operating runs from internal program memory into external one. this bit should be clear ed via software. 5 lduen updating ldrom e nable 0 = ldrom is inhibited to be erased or programmed when aprom code runs. ldrom remains read - only. 1 = ldrom is allowed to be fully accessed when aprom code runs. 4:2 - reserved 1 bs boot select ion there are different meanings of writing to or reading from this bit. writing it defines from which block mcu boots after all resets. 0 = the next rebooting will be from aprom. 1 = the next rebooting will be from ldrom. reading it indicates from which block mcu booted after previous reset. 0 = the previous rebooting is from aprom. 1 = the previous rebooting is from ldrom. 0 ispen isp e nable N79E845/844/8432 data s heet april 23 201 4 page 139 of 183 revision a2. 6 bit name description 0 = enable isp function. 1 = disable isp function. to enable isp function will start the internal 22.1184 mhz rc oscillator for timing control. to clear ispen should always be the last instruction after isp operation to stop internal rc for reducing power consumption. ispcn ? isp control 7 6 5 4 3 2 1 0 isp a17 isp a16 foen fcen fctrl.3 fctrl.2 fctrl.1 fctrl.0 r/w r/w r/w r/w r/w r/w r/w r/w address: afh reset value: 0011 0000b bit name description 7:6 ispa[17:16] isp c ontrol this byte is for isp controlling command to decide isp destinations and actions . 5 foen 4 fcen 3:0 fctrl[3:0] ispah ? isp address high byte 7 6 5 4 3 2 1 0 ispa [ 15 : 8 ] r/w address: a 7 h reset value: 0000 0000b bit name description 7:0 ispa[15:8] isp address h igh b yte ispah contains address ispa[15:8] for isp operations. ispal ? isp address low byte 7 6 5 4 3 2 1 0 ispa[7:0] r/w address: a6h reset value: 0000 0000b bit name description 7:0 ispa[7:0] isp a ddress l ow b yte ispal contains address ispa[7:0] for isp operations. N79E845/844/8432 data s heet april 23 201 4 page 140 of 183 revision a2. 6 ispfd ? isp flash data 7 6 5 4 3 2 1 0 ispfd[7:0] r/w address: aeh reset value: 0000 0000b bit name description 7:0 ispfd[7:0] isp f lash d ata this byte contains flash data which is read from or is going to be written to the flash memory. the user should write data into ispfd for program mode before triggering isp processing and read data from ispfd for read/verify mode after isp processing is fi n- ished. isptrg ? isp trigger ( ta p rotected ) 7 6 5 4 3 2 1 0 - - - - - - - ispgo - - - - - - - w address: a4h reset value: 0000 0000b bit name description 0 ispgo isp begin isp begins by setting this bit as logic 1. after this instruction, the cpu holds the program counter (pc) and the isp hardware automation takes over to control the progress. after isp action completed, the program counter continues to run the following instructions. the ispgo bit will be automatically cleared and a l- ways read as logic 0. N79E845/844/8432 data s heet april 23 201 4 page 141 of 183 revision a2. 6 20.2 isp command table isp command ispcn ispah, ispal a[15:0] ispfd d[7:0] a17, a16 foen fcen fctrl[3:0] read company id x, x [1] 0 0 1011 x [1] data out d[7:0] =dah ap rom & data flash flash page erase 0, 0 1 0 0010 a ddress i n a[15:0] x [1] flash program 0, 0 1 0 0 001 a ddress i n a[15:0] data in d[7:0] flash read 0, 0 0 0 0000 a ddress i n a[15:0] data out d[7:0] ld rom flash page erase 0, 1 1 0 0010 a ddress i n a[15:0] x [1] flash program 0, 1 1 0 0 001 a ddress i n a[15:0] data in d[7:0] flash read 0, 1 0 0 0000 a ddress i n a[15:0] data out d[7:0] config [2] page erase 1, 1 1 0 0010 a ddress i n a[15:0]=0000h x [1] config [2] program 1, 1 1 0 0001 a ddress i n a[15:0] data in d[7:0] config [2] read 1, 1 0 0 0000 a ddress i n a[15:0] data out d[7:0] note: [1] ?x? means ? don?t care ?. [2] the ? config ? means the mcu hardware configuration. [3] each page has 128 bytes. so, the address for page erase should be 0000, 0080h, 0100h, 0180h, 0200h, .., which is incremented by 0080h. N79E845/844/8432 data s heet april 23 201 4 page 142 of 183 revision a2. 6 20.3 access t able of i sp programming destination unlock lock isp c ode r esidence isp c ode r esidence aprom ldrom aprom ldrom aprom ldrom [1] [1] data flash configs [2] [2] id (read) block color comment fully accessing read only accessing inhibit [1] ldue should be 1, or it will be read only . [2] new config functions after por, wdt, reset pin or software reset note : i. config full accessing by ld rom while lock. ii. inhibit ap rom j u mp to ld rom or ld rom jump to ap rom . iii. mcu run in aprom cannot read configs. 20.4 isp u ser guide isp facilitates the updating flash contents in a convenient way; however, the user should follow some restricted laws in order that the isp operates correct ly . without notic ing warnings will possible cause undetermined results even serious damages of devic es. be attention of these notices. furthermore, t his paragraph will also support useful suggestions during isp procedures. (1) if no more isp operation need s , the user should c lear ispen (chpcon.0 ) to zer o. it will make the system void to trigger isp unawa re. furthermore, isp requires internal 22.1184 mhz rc oscillator running. if the external clock source is chosen, disabling isp will stop internal 22.1184 mhz rc for sav ing power consumption. note that a write to ispen is ta protect ed . ( 2 ) config byte s can be isp fully accessed only when loader code executing in ldrom. new config byte s other than cbs bit activate after all resets . new cbs bit activates after resets other than software reset. N79E845/844/8432 data s heet april 23 201 4 page 143 of 183 revision a2. 6 ( 3 ) when the lock bit ( config0 .1 ) is activated, isp reading, writing, or erasing can still be valid . ( 4 ) isp works under v dd = 3.0 v ~ 5.5v. ( 5 ) aprom and ldrom can read itself through isp method. note : if the user would like to develop isp program, always erase and program config bytes at the last step for data security. 20.5 isp demo code common subroutine for isp enable_isp: mov ispcn,#00110000b ;select ?standby? mode clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;chpcon is ta-protection mov ta,#55h ; orl chpcon,#00000001b ;ispen=1, enable isp function setb ea call trigger_isp ; ret disable_isp: mov ispcn,#00110000b ;select ?standby? mode call trigger_isp ; clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;chpcon is ta-protection mov ta,#55h ; anl chpcon,#11111110b ;ispen=0, disable isp function setb ea ret trigger_isp: clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;isptrg is ta-protection mov ta,#55h ; mov isptrg,#00000001b ;write ?1? to bit ispgo to trigger an isp processing setb ea ret read company id call enable_isp mov ispcn,#00001011b ;select ?read company id? mode call trigger_isp mov a,ispfd ;now, ispfd contains company id (should be dah), move to acc for ;further use call disable_isp read device id call enable_isp N79E845/844/8432 data s heet april 23 201 4 page 144 of 183 revision a2. 6 mov ispcn,#00001100b ;select ?read device id? mode mov ispah,#00h ;fill address with 0000h for low-byte did mov ispal,#00h ; call trigger_isp mov a,ispfd ;now, ispfd contains low-byte did, move to acc for further use mov ispah,#00h ;fill address with 0001h for high-byte did mov ispal,#01h ; call trigger_isp mov a,ispfd ;now, ispfd contains high-byte did, move to acc for further use call disable_isp f lash page erase (target address in aprom/ data fl ash /ldrom area) call enable_isp mov ispcn,#00100010b ;select ?flash page erase? mode, (a17,a16)=(0,0) for aprom/data ;flash/ldrom mov ispah,#??h ;fill page address mov ispal,#??h call trigger_isp call disable_isp flash program (target address in apr om/ data flash /ldrom area) call enable_isp mov ispcn,#00100001b ;select ?flash program? mode, (a17,a16)=(0,0) for aprom/data ;flash/ldrom mov ispah,#??h ;fill byte address mov ispal,#??h mov ispfd,#??h ;fill data to be programmed call trigger_isp call disable_isp flash read (target address in aprom/ data flash /ldrom area) call enable_isp mov ispcn,#00000000b ;select ?flash read? mode, (a17,a16)=(0,0) for aprom/data ;flash/ldrom mov ispah,#??h ;fill byte address mov ispal,#??h call trigger_isp mov a,ispfd ;now, ispfd contains the flash data, move to acc for further use call disable_isp config page erase (target address in config area) call enable_isp mov ispcn,#11100010b ;select ?config page erase? mode, (a17,a16)=(1,1) for config mov ispah,#00h ;fill page address #0000h, because there is only one page mov ispal,#00h call trigger_isp call disable_isp config program (target address in config area) call enable_isp mov ispcn,#11100001b ;select ?config program? mode, (a17,a16)=(1,1) for config mov ispah,#00h ;fill byte address, 0000h/0001h/0002h/0003h for config0/1/2/3, ;respectively N79E845/844/8432 data s heet april 23 201 4 page 145 of 183 revision a2. 6 mov ispal,#??h mov ispfd,#??h ;fill data to be programmed call trigger_isp call disable_isp config read (target address in config area) call enable_isp mov ispcn,#11000000b ;select ?config read? mode, (a17,a16)=(1,1) for config mov ispah,#00h ; fill byte address, 0000h/0001h/0002h/0003h for config0/1/2/3, ;respectively mov ispal,#??h call trigger_isp mov a,ispfd ;now, ispfd contains the config data, move to acc for further ;use call disable_isp N79E845/844/8432 data s heet april 23 201 4 page 146 of 183 revision a2. 6 21 power management the N79E845/844/8432 ha s several features that help the user to control the power consumption of the device. the power saved features have power - down mode and idle mode operation s . for a stable current consumption, user should watch out for the states of p0 pins. in system power saving modes, user should specifically watch out for the watchdog timer. the hardware will clear wdt counter automatically after entering into or being wo ken - up from idle or power - down mode . it prevents unconscious sy s- tem reset. pcon ? power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 1 pd power - down m ode setting this bit puts mcu into power - down mode . under this mode, both cpu and peripheral clocks stop and program counter (pc) suspends. it provides the lowest power consumption. after cpu is woken up from power down, this bit will be a u- tomatically cleared via hardware and the program continue executin g the interrupt service routine (isr) of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the instruction which fo l- lows the instruction that put the system into power - down mode . note : if idl bit and pd bit are set simultaneously, the mcu will enter into power - down mode . then it does not go to idle mode after exiting power down. 0 idl idle m ode setting this bit puts mcu into idle mode. under this mode, the cpu clock stops and program counter (pc) suspends. after cpu is woken up from idle, this bit will be automatically cleared via hardware and the program continue executing the isr of the very interrupt source that woke the system up before. after return from the isr, the device contin ues execution at the instruction which follows the i n- struction that put the system into idle mode. 21.1 idle mode idle mode suspends cpu processing by holding the program c ounter. no program code are fetched and run in idle mode. this forces the cpu state to b e frozen. the program counter (pc), the stack pointer (sp), the program status word (psw), the accumulator (acc) , and the other registers hold their contents during idle mode . the port pins hold the log i- N79E845/844/8432 data s heet april 23 201 4 page 147 of 183 revision a2. 6 cal states they had at the time idle was activated. g enerally it saves considerable power of typical ha lf of the full operating power. since the clock provided for peripheral function logic circuit like timer or serial port still remain in idle mode , the cpu can be released from the idle mode using any of the interrupt sources if enabled. the user can put the device into i dle mode by writing 1 to the bit idl ( pcon.0 ) . the instruction that sets the idl bit is the last instruction that will be execu t- ed before the device goes into idle m ode. the idle mode can be terminated in two ways. first, any interrupt if enabled will cause an exit. this will automatically clear the idl bit, terminate the idle mode , and the i nterrupt s ervice r outine (isr) will be e xecuted. after using the reti instruction to jump out of the isr, execution of the program will be the one following the instruction which put the cpu into idle mode. the second way to terminate the idle mode is wit h any reset other than software reset. 21.2 p ower - d own mode power - down mode is the lowest power state that N79E845/844/8432 can enter. it remain the power consumption as a a level. this is achieved by stopping the clock system no matter internal rc clock or external crystal. both of cpu and periph eral functions like timers or uart are frozen. flash memory stops. all activity is completely stopped and the power consumption is reduced to the lowest possible value. the device can be put into power - down mode by writing 1 to bit pd (pcon.1). the instruc tion that does this action will be the last instruction to be executed before the device goes into power - down mode . in power - down mode , ram maintains its content. the port pins output the values held by their respective. there are two ways to exit N79E845/844/8432 from power - down mode . the f irst is with all resets except software reset. bod reset will also wake up cpu from power - down mode . make sure that bod detection is enabled before the system enters into power - d own. however, for a principle of l east power consumption, it is uncommon to enable bod detection in power - down mode , which is not a recommended application. of course , the rst pin reset and power - on reset will remove the power down status. after rst pin reset or power - on reset , t he cpu is initialized and start s executing program code from the beginning. the N79E845/844/8432 can be woken up from power - down mode by forcing an external interrupt pin activated, provi d- ing the corresponding interrupt enabled and the global enable ea bit (ie.7) is set. if these conditions are met, the trigger on the external pin will asynchronously restart the clock system. then device executes the interrupt service routine (isr) for the corresponding external interrupt. after the isr is completed, the program exec ution returns to the instruction after the one that put s the device into power - down mode and continues. bod , w at ch dog and kbi interrupt are other source s to wake up cpu from power down. as mentioned before the user will endure the current of bod detection circui t. using kbi interrupt to wake up cpu from power down has a r e- N79E845/844/8432 data s heet april 23 201 4 page 148 of 183 revision a2. 6 striction : the kbi pin keeps low (high) before cpu enters power down. then o nly rising (falling) edge of kbi interrupt can wake up cpu fr om power down. N79E845/844/8432 data s heet april 23 201 4 page 149 of 183 revision a2. 6 22 clock system the N79E845/844/8432 provide s three options of the clock system source that is configured by f osc (config3.1~0). it switches the clock system from crystal/resonator, on - chip rc oscillator, or external clock from xtal1 pin. the N79E845/844/8432 is embed ded with an on - chip rc o scillator of 22.1184 mhz/11.0592 mhz selected by config se t- ting, factory trimmed to 1% under the condition of room temperature and v dd =5v. if the external clock source is from the crystal, the frequency supports from 4 mhz to 24 mhz. oscillating circuit internal rc oscillator (22.1184mhz) xtal2 xtal1 1/2 fosc[1:0] (config3[1:0]) oscfs (config3.3) f osc 1 0 0x 10 turbo 8051 cpu timers serial port (uart) i 2 c pwm internal rc oscillator (~10khz) flash f ihrc f ilrc 11 clock divider f sys watchdog timer adc divm clock filter ckf (config3.4) kbi figure 22? 1 clock system block diagram N79E845/844/8432 data s heet april 23 201 4 page 150 of 183 revision a2. 6 config3 7 6 5 4 3 2 1 0 cwdten - - ckf oscfs - fosc1 fosc0 r/w - - r/w r/w - r/w r/w u programmed value: 1111 1111b bit name description 4 ckf clock f ilter e nable 1 = enable clock filter. it increases noise immunity and emc capacity. 0 = disable clock filter. 3 oscfs internal rc o scillator f requency s elect ion 1 = select 22.1184 mhz as the clock system if internal rc oscillator mode is used. it bypasses the divided -by - 2 path of internal oscillator to select 22.1184 mhz output as the clock system source. 0 = select 11.0592 mhz as the clock system if internal rc oscillator mode is used. the internal rc divided - by - 2 path is selected. the internal oscillator is equiv a- lent to 11.0592 mhz output used as the clock system. 2 - reserved 1:0 fosc1 fosc0 oscillator s elect b it for c hip c lock s ource s elect ion, refer to the following table. (fosc1, fosc0) chip c lock s ource (1, 1) internal rc oscillator (1, 0) reserved (0, 1) (0, 0) external crystal, 4 mhz ~ 24 mhz divm ? clock divider register 7 6 5 4 3 2 1 0 divm[7:0] r/w address: 95h reset value: 0000 0000b bit name description 7:0 divm[7:0] clock d vider the clock system frequency f sys follows the equation below according to divm value. f sys = f osc , while divm = 00h. f sys = ) 1 + divm ( 2 1 f osc, while divm = 01h ~ ffh. N79E845/844/8432 data s heet april 23 201 4 page 151 of 183 revision a2. 6 22.1 on - chip rc oscillator the on - chip rc oscillator is enabled while fosc (config3.1~0) is 1. setting oscfs (config3.3) logic 1 will switch to a divided - by - 2 path . 22.2 crystal/resonator the crystal/resonator is selected as the system clock while fosc[1:0] keep programmed as [0:1]. xtal1 and xtal2 are the input and output, respectively, of an internal inverting ampli fier. a crystal or resonator can be used by connecting b e- tween xtal1 and xtal2 pins. the crystal or resonator frequency from 4mhz up to 24mhz is allowed. ckf (config3.4) is the control bit of clock filter circuit of xtal1 input pin. N79E845/844/8432 data s heet april 23 201 4 page 152 of 183 revision a2. 6 23 power monitoring to prevent incorrect execution during power up and power drop, the N79E845/844/8432 provides three power monitor function s, p ower - on detect ion and bod detect ion . 23.1 power - o n detect ion the power - on detect ion function is design ed for detect ing power up after powe r voltage reaches to a level where system can work . after power - on detect ed , the po f (pcon. 4) will be set 1 to indicate a cold reset, a power - on reset complete. the p of flag can be cleared via software. 23.2 brown - out detect ion the other power monitoring function, bod detection circuit is for monitoring the v dd level during execution. there are two programmable bod trigger levels available for wide voltage applications. th e two nominal levels are 2. 7 v and 3.8 v selected via setting cbov i n config2 . when v dd drops to the selected bod trigger level ( v bod ), the bod detection logic will either reset the cpu or request a bod interrupt. the use r may determine bod reset or interrupt enable accor d- ing to different application system s . the bod detection will request the interrupt while v dd drops below v bod while borst (pmcr.4) is 0. in this case, bof (pmcr.3) will set as 1. after the user clear s this flag whereas v dd remains below v bod , bof will not set again. bof just acknowledge the user a power drop occurs. the bof will set 1 after v dd goes higher than v bod to indicate a power resuming. v bod has a hysteresis of 20~200mv. config2 7 6 5 4 3 2 1 0 c bod en cbov - c borst - - - - r/w r/w - r/w - - - - unprogrammed value: 1111 1111b bit name description 7 cboden config bod d etect ion e nable 1 = dis able bod detection . 0 = en able bod detection . boden is initialized by inverted cboden (config2, bit - 7) at any resets. N79E845/844/8432 data s heet april 23 201 4 page 153 of 183 revision a2. 6 bit name description 6 cbov config bod v oltage s elect ion this bit select one of two bod voltage level. config - bits cbov sfr bov bod voltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 cborst config bod r eset e nable this bit decides if a bod reset is caused after a bod event. 1 = enable bod reset when v dd drops below v bod or v dd rises above v bod . 0 = disable bod reset when v dd drops below v bod. chip will assert bof when v dd drops below v bod or v dd rises above v bod . pmc r ? power monitoring control ( ta protected ) 7 6 5 4 3 2 1 0 boden bov - borst bof - - - r/w r/w - r/w r/w - - - address: a 3 h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7 boden bod - detect f unction c ontrol boden is initialized by inverted cboden (config2, bit - 7) at any resets. 1 = en able bod detection . 0 = dis able bod detection . 6 bov bod v oltage s elect b its bod are initialized at reset with the value of bits cbov in config3 - bits bod voltage select bits: config - bits cbov sfr bov bod v oltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved N79E845/844/8432 data s heet april 23 201 4 page 154 of 183 revision a2. 6 bit name description 4 borst bod r eset e nable this bit decides if a bod reset is caused after a bod event. 0 = disable bod reset when v dd drops below v bod or v dd rises above v bod . chip will assert bof when v dd drops below v bod. 1 = enable bod reset when v dd drops below v bod or v dd rises above v bod . 3 bof bod f lag this flag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (ie.5) and ea (ie.7) are set, a bod inte r- rupt requirement will be generated. this bit should be cleared via software. 2 - it should be set to logic 0. 1 - reserved 0 - reserved note : i f bof is 1 after chip reset, it is strongly recommended to initialize the user program by clearing bof. N79E845/844/8432 data s heet april 23 201 4 page 155 of 183 revision a2. 6 24 reset conditions the N79E845/844/8432 has several options to place device in reset condition. in general, most sfrs go to their reset va l- ue irrespective of the reset condition, but there are sever al reset source indicat ion flags whose state depends on the s ource of reset. t here are 5 ways of putting the device into reset state. they are power - on reset, rst pin reset , software reset, watchdog timer reset , and bod reset. 24.1 power - o n reset the N79E845/844/8432 incorporate s an internal voltage reference . during a power - on process of rising power supply voltage v dd , this voltage reference will hold the cpu in power - on reset mode when v dd is lower than t he voltage refe r- ence threshold. this design make s cpu not access program flash while the v dd is not adequate performing the flash rea d- ing. if a n undetermined operating code is read from the program flash and executed, this will put cpu and even the whole system in to an erroneous state. after a whil e, v dd rises above the reference threshold where the system can work , the selected oscillator will star t and then program code will be executed from 0000h. at the same t ime, a power - on flag pof (pcon.4) will be set 1 to indicate a cold reset, a power - on re set complete. note that the contents of internal ram will be undetermined after a power - on. it is recommended that user give initial values for the ram block. p1.6, p1.7, p1.0 and p1.1 are forced to quasi - bi - direction type when chip is in reset state. it is recommended that t he pof be cleared to 0 via software to check if a cold reset or warm reset performed after the next reset occurs. if a cold reset caused by power off and on, pof will be set 1 again. if the reset is a warm reset caused by other reset s ources, pof will remain 0. the user may take a different course to check other reset flags and deal with the warm reset event. pcon ? power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 4 pof power - on r eset f lag this bit will be set as 1 after a power - on reset. it indicates a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommended to be cleared via software. N79E845/844/8432 data s heet april 23 201 4 page 156 of 183 revision a2. 6 24.2 bod reset bod detection circuit is for monitoring the v dd level during execution. when v dd drops to the selected bod trigger level (v bod ) or v dd rises over v bod , the bod detection logic will reset the cpu if borst (pmcr.4) setting 1. pmcr ? power monitoring control ( ta p rotected ) 7 6 5 4 3 2 1 0 boden bov - borst bof - - - r/w r/w - r/w r/w - - - address: a3h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7 boden bod - detect f unction c ontrol boden is initialized by inverted cboden (config2, bit - 7) at any resets. 1 = en able bod detection . 0 = dis able bod detection . 6 bov bod v oltage s elect b its bod are initialized at reset with the value of bits cbov in config3 - bits bod voltage select bits: config - bits cbov sfr bov bod v oltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 borst bod r eset e nable this bit decides if a bod reset is caused after a bod event. 0 = disable bod reset when v dd drops below v bod or v dd rises above v bod . chip will assert bof when v dd drops below v bod. 1 = enable bod reset when v dd drops below v bod or v dd rises above v bod . 3 bof bod f lag this flag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (ie.5) and ea (ie.7) are set, a bod inte r- rupt requirement will be generated. this bit should be cleared via software. 2 - it should be set to logic 0. 1 - reserved 0 - reserved N79E845/844/8432 data s heet april 23 201 4 page 157 of 183 revision a2. 6 24.3 rst p in reset the hardware reset input is rst pin which is the input with a schmitt trigger. a hardware reset is accomplished by hol d- ing the rst pin low for at least two machine - cycles to ensure detection of a valid hardware reset signal. the reset circui t- ry then synchronously applies the internal reset signal. thus the reset is a synchronous operation and requires t he clock to be running to cause an external reset. once the device is in reset condition, it will remain so as long as rst pin is 1. after the rst low is removed, the cpu will exit the reset state with in two machine - cycles and begin code executing from ad dress 0000h. there is no flag assoc i- ated with the rst pin reset condition. however since the other reset sources have flags, the external reset can be consi d- ered as the default reset if those reset flags are cleared. if a rst pin reset applies while cpu is in power - down mode , the way to trigger a hardware reset is slightly different. since the power - down mode stops clock system, the reset signal will asynchronously cause the clock system resuming. after the clock system is stable, cpu will enter into the re set state, then exit and start to execute program code from a d- dress 0000h. note: because reset pin has internal pull - up resistor (about 200k at v dd = 5v), this pin cannot be floating. reset pin should be connect ed to a 100 pull - up resistor and a 10 uf pull - low capacitor. 24.4 watchdog timer reset the watchdog timer is a free running timer with programmable time - out intervals. the user can clear the watchdog timer at any time, causing it to restart the count. when the selected time - out occurs, the watchdog t imer will reset the system directly. the reset condition is maintained via hardware for two machine - cycles. after the reset is removed the device will begin execution from 0000h. once a reset due to watchdog timer occurs the watchdog timer reset flag wdtrf (wdcon0.3) will be set. this bit keeps unchanged after any reset other than a power - on reset. the user may clear wdtrf via software. N79E845/844/8432 data s heet april 23 201 4 page 158 of 183 revision a2. 6 wdcon0 ? watchdog timer control ( ta p rotected ) 7 6 5 4 3 2 1 0 wdten wdclr wdtf widpd wdtrf wps2 wps1 wps0 r/w w - r/w r/w r/w r/w r/w address: d8h reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 3 wdtrf wdt r eset f lag when the mcu resets itself, this bit is set by hardware. the bit should be cleared by sof t- ware. if ewrst=0, the interrupt flag wdtrf won?t be set by hardware, and the mcu will reset itself right away. if ewrst=1, the interrupt flag wdtrf will be set by hardware and the mcu will jump into wdt?s interrupt service routine if wdt interrupt is enabled, and the mcu won?t reset itself until 512 cpu clocks elapse. in other words, in this condition, the user also needs to clear the wdt counter (by writing ?1? to wdclr bit) during this period of 512 cpu clocks, or the mcu will also reset itself when 512 cpu clocks elapse. wdcon1 ? watchdog timer control ( ta p rotected ) 7 6 5 4 3 2 1 0 - - - - - - - ewrst - - - - - - - r/w address: abh reset value: 0000 0000b bit name description 0 ewrst 0 = disable wdt reset function. 1 = enable wdt reset function. 24.5 software reset N79E845/844/8432 are enhanced with a software reset. this allows the program code to reset the whole system in sof t- ware approach. it is quite useful in the end of an isp progress. for example, if an ldrom updating aprom isp finishes and the code in aprom is correctly upda ted, a software reset can be asserted to reboot cpu from the aprom to check the result of the updated aprom program code immediately. writing 1 to swrst (chpcon.7) will trigger a software reset. note that this bit is timed access protection. see demo code below. N79E845/844/8432 data s heet april 23 201 4 page 159 of 183 revision a2. 6 chpcon ? chip control ( ta p rotected ) 7 6 5 4 3 2 1 0 swrst ispf lduen - - - bs ispen w r/w r/w - - - r/w r/w address: 9fh reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 7 swrst software r eset setting this bit as logic 1 will cause a software reset. it will automatically be cleared via hardware after reset in finished. the software demo code is listed below. clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;ta protection. mov ta,#55h ; anl chpcon,#0fdh ;bs = 0, reset to aprom. mov ta,#0aah mov ta,#55h orl chpcon,#80h ;software reset 24.6 boot sele ct ion rst-pin reset brownout reset software reset power-on reset load reset and boot from ldrom reset and boot from aprom config0.7 chpcon.1 watchdog timer reset bs cbs bs = 0 bs = 1 figure 24? 1 boot select ion diagram the N79E845/844/8432 provides user a flexible boot selection for variant application. the sfr bit bs in chpcon.1 determines cpu boot ing from ap rom or ld rom after any source of reset . if reset occurs and bs is 0 , cpu will re boot from ap prom . else, the cpu will re boot from ld rom . N79E845/844/8432 data s heet april 23 201 4 page 160 of 183 revision a2. 6 config0 7 6 5 4 3 2 1 0 cbs - - - - - lock dfen r/w - - - - - r/w r/w unprogrammed value: 1111 1111b bit name description 7 cbs config b oot s elect ion this bit defines from which block mcu boots after all resets except software reset. 1 = mcu will boot from aprom after all resets except software reset . 0 = mcu will boot from ldrom after all resets except software reset . chpcon ? chip control ( ta p rotected ) 7 6 5 4 3 2 1 0 swrst ispf lduen - - - bs [1] ispen w r/w r/w - - - r/w r/w address: 9fh reset value: see table 7 ? 2 N79E845/844/8432 sfr description and reset values bit name description 1 bs boot s elect ion there are different meanings of writing to or reading from this bit. writing: it defines from which block mcu boots after all resets. 0 = the next rebooting will be from aprom. 1 = the next rebooting will be from ldrom. reading: it indicates from which block mcu booted after previous reset. 0 = the previous rebooting is from aprom. 1 = the previous rebooting is from ldrom. [1] note that this bit is initialized by being loaded from the inverted value of cbs bit in config0.7 at all resets except software reset. it keeps unchanged after software reset. note : a fter the cpu is released from all reset state, the hardware will always check the bs bit instead of the cbs bit to determine from aprom or ldrom that the device reboots. 24.7 reset state the reset state does not affect the on - chip ram. the data in the ram will be preserved during the reset. note that the ram contents may be lost if the v dd falls below approximately 1.2 v. this is the minimum voltage level required for N79E845/844/8432 data s heet april 23 201 4 page 161 of 183 revision a2. 6 ram data retention. therefore , after the power - on reset the ram contents will be in determinate. during a power fail condition . if the power falls below the data retention minim um voltage , the ram contents will also los e . after a reset, most of sfrs go to their initial value s except bits which are affected by different reset events. see the note s of table 7 ? 2 N79E845/844/8432 sfr description and reset values . for the initial state of all sfrs. some special fun c- tion registers initial value depends on different reset sources. refer to table 24 - for detail s . the program counter is forced to 0000h and held as long as the reset condition is applied. note that the s tack p ointer is also reset to 07 h , therefore the stack contents ma y be effectively lost during the reset event even though the ram contents are not altered. after a r eset, i nterrupts and timers are disabled. the watchdog t imer is disabled if the reset source was a power - on reset . the i/o port sfrs have ff h written into t hem which puts the port pins in a high state. table 24 - 2 initial state of sfr caused by different resets power - on reset watchdog reset sof t ware/ external reset bod reset with time a c cess protection wdcon 0 (d8h) c000 0000b b7(enwdt)= /cenwdt( config3 .7) c0uu 1uuub c 0uu uuuub y wdcon1 (abh) 0000 0000b y isptrg (a4h) xxxx xxx0b y pmcr (a3h) c x cc 10xxb b[7:4]= config2 u x uu u0xxb u x uu 10xxb y chpcon (9fh) 0000 00c0b b1(bs)=/cbs 000x xuu0b y shbda (9ch) config1 unchanged y pcon (87h) 0001 000b 00uu 0000b 00uu 0000b ( software /external reset) 00uu 0000b n note: the writes of aah and 55h should occur within 3 machine - cycles of each other. interrupts should be disabled during this procedure to avoid delay between the two writes. N79E845/844/8432 data s heet april 23 201 4 page 162 of 183 revision a2. 6 25 config bit s ( config ) the N79E845/844/8432 has several hardware configuration bytes , called config bits , which are used to configure the hardware option s such as the security bits, clock system source , and so on , which hardware options can be re - configured through the programmer/wr iter or isp modes. the N79E845/844/8432 has four config bits those are config0 ~ 3. several functions which are defined by certain config bits are also available to be re - configured by certain sfr bits. therefore, there is a need to load such config bits into respective sfr bits. such loading will occurs after reset s . (software reset will reload all config bits except cbs bit in config0 . 7 ) these sfr bits can be continuously co n- trolled via user?s software. other resets will remain the values in these sfr bits unchanged. note : config bits marked as " - " should always keep unprogrammed. 25.1 config0 7 6 5 4 3 2 1 0 cbs - - - - - lock dfen r/w - - - - - r/w r/w unprogrammed value: 1111 1111b bit name description 7 cbs config b oot s elect ion this bit defines from which block mcu boots after all resets except software r e- set. 1 = mcu will boot from aprom after all resets except software reset. 0 = mcu will boot from ldrom after all resets except software reset. 6 :2 - reserved 1 lock chip l ock e nable 1 = chip is unlocked. all of aprom, ldrom , and data flash are not locked . their contents can be read out through a parallel programmer/writer. 0 = chip is locked. aprom, ldrom, and data flash are locked. their contents read through parallel programmer/writer w ill become ffh. note that config bytes are always unlocked and can be read. hence, once the chip is locked, the config bytes cannot be erased or programmed individually. the only way to disable chip lock is to use the whole chip erase mode. however, all da ta within aprom, ldrom, data flash, and other config bits will be erased when this proc e- dure is executed. if the chip is locked, it does not alter the isp function. N79E845/844/8432 data s heet april 23 201 4 page 163 of 183 revision a2. 6 bit name description 0 dfen data flash e nable ( n79e8 4 5 o nly) 1 = there is no data flash space. the aprom size is 16 k byte s . 0 = data flash exists. the data flash and aprom share 16 kbytes depending on shbda setting s . chpcon config 0 cbs 7 - 6 4 - 5 - 3 - 2 lock 1 dfen 0 swrst 7 ispf 6 ldue 5 - 4 - 3 - 2 bs 1 ispen 0 - figure 25? 1 config0 reset reload ing except software reset 25.2 config1 ( N79E845 only) 7 6 5 4 3 2 1 0 chbda[7:0] [1] r/w unprogrammed value: 1111 1111b bit name description 7:0 chbda[7:0] config h igh b yte of data flash s tarting a ddress this byte is valid only when dfen (config0.0) is 0. it is used to determine the starting address of the data flash. note : t here will be no aprom if setting chbda 00h. cpu will execute codes in minimum size(256b) of internal program memory. shbda config 1 shbda[7:0] 7 6 5 4 3 2 1 0 chbda[7:0] 7 6 5 4 3 2 1 0 figure 25? 2 config1 reset reloading N79E845/844/8432 data s heet april 23 201 4 page 164 of 183 revision a2. 6 25.3 config2 7 6 5 4 3 2 1 0 c bod en cbov - c borst - - - - r/w r/w - r/w - - - - unprogrammed value: 1111 1111b bit name description 7 cboden config bod d etect ion e nable 1 = dis able bod detection . 0 = en able bod detection . boden is initialized by inverted cboden (config2, bit - 7) at any resets. 6 cbov config bod v oltage s elect ion this bit selects one of two bod voltage level. config - bits cbov sfr bov bod v oltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 cborst config bod r eset e nable this bit decides if a bod reset is caused after a bod event. 1 = enable bod reset when v dd drops below v bod or v dd rises above v bod. 0 = disable bod reset when v dd drops below v bod or v dd rises above v bod . 3:0 - reserved pmcr config 2 cboden 7 cbov 6 5 cborst 4 - 3 - 2 - 1 - 0 boden 7 bov 6 5 borst 4 bof 3 - 2 - 1 - 0 - - figure 25? 3 config2 reset reload ing N79E845/844/8432 data s heet april 23 201 4 page 165 of 183 revision a2. 6 25.4 config3 7 6 5 4 3 2 1 0 cwdten - - ckf oscfs - fosc1 fosc0 r/w - - r/w r/w - r/w r/w unprogrammed value: 1111 1111b bit name description 7 cwdten config watchdog timer e nable 1 = dis able watchdog timer after all resets . 0 = en able watchdog timer after all resets . wdten is initialized by inverted cwdten (config3, bit - 7) at any other resets. 6 - reserved 5 - reserved 4 ckf clock f ilter e nable 1 = enable clock filter. it increases noise immunity and emc capacity. 0 = disable clock filter. 3 oscfs internal rc o scillator f requency s elect ion 1 = select 22.1184 mhz as the clock system if internal rc oscillator mode is used. it bypasses the divided -by - 2 path of internal oscillator to select 22.1184mhz output as the clock system source. 0 = select 11.0592 mhz as the clock system if internal rc oscillator mode is used. the internal rc divided - by - 2 path is selected. the internal oscillator is eq uiv a- lent to 11.0592 mhz output used as the clock system. 2 - reserved 1 fosc1 oscillator s elect b it chip c lock s ource s elect ion (s ee the f ollowing t able ) (fosc1, fosc0) chip c lock s ource (1, 1) internal rc oscillator (1, 0) reserved (0, 0) (0, 1) external crystal, 4 mhz ~ 24 mhz 0 fosc0 N79E845/844/8432 data s heet april 23 201 4 page 166 of 183 revision a2. 6 wdcon0 config3 cwdten 7 6 - 5 ckf 4 oscfs 3 - 2 fosc1 1 0 wdten 7 wdclr 6 wdtf 5 widpd 4 wdtrf 3 wps2 2 wps1 1 wps0 0 fosc0 - figure 25? 4 config3 reset reloading N79E845/844/8432 data s heet april 23 201 4 page 167 of 183 revision a2. 6 26 instruction set s the N79E845/844/8432 execute s all the instructions of the standard 8051 family. all instructions are coded within an 8 - bit field called an opcode. this single byte should be fetched from program memory. the opcode is decoded by the cpu. it determines what action the microcontroller wi ll take and whether more operation data is needed from memory. if no other data is needed, then only one byte was required. thus the instruction is called a one byte instruction. in some cases, more data is needed , which will be two or three byte instructi ons. table 26? 1 lists all instructions in details. the n ote of the instruction set s and addressing modes are shown below. rn (n = 0~7) register r0~r7 of the currently selected register bank. direct 8 - bit in ternal data location?s address. this could be an internal data ram l o- cation (0~127) or a sfr (e.g. i/o port, control register, status register, etc.) (128~255). @ri (i = 0, 1) 8 - bit internal data ram location (0~255) addressed indirectly through regis - ter r0 or r1. #data 8 - bit constant included in the instruction. #data16 16- bit constant included in the instruction. addr16 16- bit destination address. used by lcall and ljmp. a branch can be any within the 16 k byte s pro gram memory address space. addr11 11- bit destination address. used by acall and ajmp. the branch will be within the same 2 k byte s page of program memory as the first byte of the following instruction. rel signed (2?s complement) 8 - bit offset byte. used by sjmp and all conditional branches. the range is - 128 to +127 bytes relative to first byte of the follow - ing instruction. bit direct addressed bit in internal data ram or sfr. table 26 ? 1 instruction set for the N79E845/844/8432 instruction opcode bytes clock c ycles N79E845/844/8432 vs. t radition 80c51 s peed r atio nop 00 1 4 3.0 add a, r n 28 ~2f 1 4 3.0 add a, @ri 26 , 27 1 4 3.0 add a, direct 25 2 8 1.5 add a, #data 24 2 8 1.5 addc a, r n 38 ~3f 1 4 3.0 addc a, @ri 36 , 37 1 4 3.0 addc a, direct 35 2 8 1.5 addc a, #data 34 2 8 1.5 subb a, r n 98 ~9f 1 4 3.0 N79E845/844/8432 data s heet april 23 201 4 page 168 of 183 revision a2. 6 table 26 ? 1 instruction set for the N79E845/844/8432 instruction opcode bytes clock c ycles N79E845/844/8432 vs. t radition 80c51 s peed r atio subb a, @ri 96 , 97 1 4 3.0 subb a, direct 95 2 8 1.5 subb a, #data 94 2 8 1.5 inc a 04 1 4 3.0 inc r n 08 ~0f 1 4 3.0 inc @ri 06 , 07 1 4 3.0 inc direct 05 2 8 1.5 inc dptr a3 1 8 3.0 dec a 14 1 4 3.0 dec r n 18 ~1f 1 4 3.0 dec @ri 16 , 17 1 4 3.0 dec direct 15 2 8 1.5 dec dptr a5 1 8 - mul ab a4 1 20 2.4 div ab 84 1 20 2.4 da a d4 1 4 3.0 anl a, r n 58 ~5f 1 4 3.0 anl a, @ri 56 , 57 1 4 3.0 anl a, direct 55 2 8 1.5 anl a, #data 54 2 8 1.5 anl direct, a 52 2 8 1.5 anl direct, #data 53 3 12 2.0 orl a, r n 48 ~4f 1 4 3.0 orl a, @ri 46 , 47 1 4 3.0 orl a, direct 45 2 8 1.5 orl a, #data 44 2 8 1.5 orl direct, a 42 2 8 1.5 orl direct, #data 43 3 12 2.0 xrl a, r n 68 ~6f 1 4 3.0 xrl a, @ri 66 , 67 1 4 3.0 xrl a, direct 65 2 8 1.5 xrl a, #data 64 2 8 1.5 xrl direct, a 62 2 8 1.5 xrl direct, #data 63 3 12 2.0 clr a e4 1 4 3.0 cpl a f4 1 4 3.0 rl a 23 1 4 3.0 rlc a 33 1 4 3.0 rr a 03 1 4 3.0 rrc a 13 1 4 3.0 N79E845/844/8432 data s heet april 23 201 4 page 169 of 183 revision a2. 6 table 26 ? 1 instruction set for the N79E845/844/8432 instruction opcode bytes clock c ycles N79E845/844/8432 vs. t radition 80c51 s peed r atio swap a c4 1 4 3.0 mov a, r n e8 ~ef 1 4 3.0 mov a, @ri e6 , e7 1 4 3.0 mov a, direct e5 2 8 1.5 mov a, #data 74 2 8 1.5 mov r n , a f8 ~ff 1 4 3.0 mov r n , direct a8 ~af 2 8 3.0 mov r n , #data 78 ~7f 2 8 1.5 mov @ri, a f6 , f7 1 4 3.0 mov @ri, direct a6 , a7 2 8 3.0 mov @ri, #data 76 , 77 2 8 1.5 mov direct, a f5 2 8 1.5 mov direct, r n 88 ~8f 2 8 3.0 mov direct, @ri 86 , 87 2 8 3.0 mov direct, direct 85 3 12 2.0 mov direct, #data 75 3 12 2.0 mov dptr, #data16 90 3 12 2.0 movc a, @a+dptr 93 1 8 3.0 movc a, @a+pc 83 1 8 3.0 movx a, @ri [1] e2 , e3 1 8 3.0 movx a, @dptr [1] e0 1 8 3.0 movx @ri, a [1] f2 , f3 1 8 3.0 movx @dptr, a [1] f0 1 8 3.0 push direct c0 2 8 3.0 pop direct d0 2 8 3.0 xch a, r n c8 ~cf 1 4 3.0 xch a, @ri c6 , c7 1 4 3.0 xch a, direct c5 2 8 1.5 xchd a, @ri d6 , d7 1 4 3.0 clr c c3 1 4 3.0 clr bit c2 2 8 1.5 setb c d3 1 4 3.0 setb bit d2 2 8 1.5 cpl c b3 1 4 3.0 cpl bit b2 2 8 1.5 anl c, bit 82 2 8 3.0 anl c, /bit b0 2 8 3.0 orl c, bit 72 2 8 3.0 orl c, /bit a0 2 8 3.0 mov c, bit a2 2 8 1.5 N79E845/844/8432 data s heet april 23 201 4 page 170 of 183 revision a2. 6 table 26 ? 1 instruction set for the N79E845/844/8432 instruction opcode bytes clock c ycles N79E845/844/8432 vs. t radition 80c51 s peed r atio mov bit, c 92 2 8 3.0 acall addr11 11, 31, 51, 71, 91, b1, d1, f1 [2] 2 12 2.0 lcall addr16 12 3 16 1.5 ret 22 1 8 3.0 reti 32 1 8 3.0 ajmp addr 11 01, 21, 41, 61, 81, a1, c1, e1 2 12 2.0 ljmp addr16 02 3 16 1.5 jmp @a+dptr 73 1 8 3.0 sjmp rel 80 2 12 2.0 jz rel 60 2 12 2.0 jnz rel 70 2 12 2.0 jc rel 40 2 12 2.0 jnc rel 50 2 12 2.0 jb bit, rel 20 3 16 1.5 jnb bit, rel 30 3 16 1.5 jbc bit, rel 10 3 16 1.5 cjne a, direct, rel b5 3 16 1.5 cjne a, #data, rel b4 3 16 1.5 cjne @ri, #data, rel b6 , b7 3 16 1.5 cjne r n , #data, rel b8 ~bf 3 16 1.5 djnz r n , rel d8 ~df 2 12 2.0 djnz direct, rel d5 3 16 1.5 [1] the most three significant bits in the 11 - bit address [a10:a8] decide the acall hex code. the code will be [a10,a9,a8,1,0,0,0,1]. [2] the most three significant bits in the 11 - bit address [a10:a8] decide the ajmp hex code. the code will be [a10,a9,a8,0,0,0,0,1]. N79E845/844/8432 data s heet april 23 201 4 page 171 of 183 revision a2. 6 27 in - circuit program (icp) the icp (in - circuit - pr ogram) mode is another approach to access the flash eprom. there are only 3 pins needed to pe r- form the icp function. one is input /rst pin, which should be fed to gnd in the icp working period. one is clock input, shared with p1.7, which accepts serial clo ck from external device. another is data i/o pin, shared with p1.6, that an exte r- nal icp program tool shifts in/out data via p1.6 synchronized with clock(p1.7) to access the flash eprom of the N79E845/844/8432 . upon entry into icp program mode, all pin will be set to quasi - bidirectional mode, and output to level ?1?. the N79E845/844/8432 supports programming of flash eprom ( 16k/8k/ 4k bytes aprom eprom) , data flash memory ( 128 bytes per page ) and ldrom . user has the option to program the aprom , data flash and ldrom. n79e84x p1.6 p1.7 vss app. device app. device app. device v dd v pp data vss icp writer tool vcc jumper icp connector system board icp power switch * * * *: resistor is optional by application * rst clock v dd figure 27? 1 icp connection with n79e84xa note: 1. when us ing icp to upgrade code, the /rst , p1.6 and p1.7 should be taken within design system board. 2. after program finished by icp, to suggest system power should power off and remove icp connector then power on. 3. it is recommended that user performs erase function and programming configure bits continuously without any interruption. N79E845/844/8432 data s heet april 23 201 4 page 172 of 183 revision a2. 6 user may refer to the following website for icp program tool. in item1, please select ? nuvoton isp - icp programmer?. 1. http://www.nuvoton.com/nuvotonmoss/community/productinfo.aspx?tp_guid=670aaf31 - 5d5c - 45d3- 8a9e - 040e148d55cf figure 27? 2 nuvoton isp - icp programmer N79E845/844/8432 data s heet april 23 201 4 page 173 of 183 revision a2. 6 28 electrical characteristics 28.1 absolute maximum ratings table 28 ? 1 absolute maximum ratings parameter rating u nit operating temperature under bias - 40 to +85 c storage temperature range - 55 to +150 c voltage on v dd pin to v ss - 0.3 to +6.5 v voltage on any other pin to v ss - 0.3 to (v dd +0.3) v stresses at or above those listed under ?absolute maximum ratings? m a y cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification i s not implied. exposure to absolute maximum rating conditions may affect d e- vice reliability. 28.2 dc electrical characteristics table 28 ? 2 operation voltage parameter sym min typ max condition unit operating voltage v dd 4.5 5.5 f osc = 4mhz ~ 24mhz v 2. 4 5.5 f osc = 4mhz ~12mhz 3.0 5.5 internal rc 22.1184mhz 2. 4 5.5 internal rc 11.0592mhz isp operating voltage v dd 3.0 5.5 f osc = 4mhz ~ 24mhz v table 28 ? 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40~85 c, unless otherwise specified. ) sym parameter test condition s min typ max unit s vdd v dd rise rate to ensure internal power - on reset signal see section on power - on reset for details 0.05 [7] - - v/ms v il input low voltage ( general purpose i/o with ttl input ) 2. 4 < v dd < 5.5v - 0.5 0.2v dd - 0.1 v N79E845/844/8432 data s heet april 23 201 4 page 174 of 183 revision a2. 6 table 28 ? 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40~85 c, unless otherwise specified. ) sym parameter test condition s min typ max unit v il 1 input low voltage ( general purpose i/o with schmitt trigger input ) 2. 4 < v dd < 5.5v - 0.5 0.3v dd v v il2 input low voltage ( / rst, xtal1 ) 2. 4 < v dd < 5.5v - 0.5 0.2v dd - 0.1 v v ih input high voltage ( general purpose i/o with ttl input ) 2. 4 < v dd < 5.5v 0.2v dd +0.9 v dd +0.5 v v ih 1 input high voltage ( general purpose i/o with schmitt trigger input ) 2. 4 < v dd < 5.5v 0.7v dd v dd +0.5 v v ih 2 input high voltage ( / rst, xtal1 ) 2. 4 < v dd < 5.5v 0.7v dd v dd +0.5 v v ol output low voltage ( general purpose i/o of p0, p3 , all modes except input only) v dd =4.5v, i ol = 20 ma [3] , [4] 0.4 5 v v dd = 3 . 0 v, i ol = 14 ma [3] , [4] 0.4 5 v v dd =2.4v, i ol = 10 ma [3], [4] 0.4 5 v v ol1 output low voltage (p10, p11, p14, p16, p17) ( all modes except input only) v dd =4.5v, i ol = 38 ma [3] , [4] 0.4 5 v v dd =3.0v, i ol = 27 ma [3] , [4] 0.4 5 v v dd =2.4v, i ol = 20 ma [3], [4] 0.4 5 v v oh output high voltage ( general purpose i/o , quasi bidire c- tional ) v dd =4.5v i oh = - 3 8 0 a [4] 2.4 v v dd = 3 . 0 v i oh = - 90 a [4] 2. 4 v v dd =2.4v i oh = - 48 a [4] 2.0 v N79E845/844/8432 data s heet april 23 201 4 page 175 of 183 revision a2. 6 table 28 ? 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40~85 c, unless otherwise specified. ) sym parameter test condition s min typ max unit v oh1 output high voltage ( general purpose i/o , push - pull ) v dd =4.5v i oh = - 2 8 .0 ma [3], [4] 2.4 v v dd = 3 . 0 v i oh = - 7 ma [3], [4] 2. 4 v v dd =2.4v i oh = - 3.5 ma [3], [4] 2.0 v i il logical 0 input current ( general purpose i/o , quasi bi - direction ) v dd =5.5v, v in =0.4v - 40 at 5.5v - 50 a i tl logical 1 to 0 transition current ( general purpose i/o , quasi bi - direction) v dd =5.5v, v in =2.0v [2] - 550 at 5.5v - 650 a i li input leakage current ( general purpose i/o , open - drain or input only) 0 < v in < v dd <1 10 a i op op current ( active mode [5] ) xtal 12mhz, v dd =5.0v 3.1 ma xtal 24mhz, v dd =5.5v 4.3 ma xtal 12mhz, v dd =3.3v 1.7 ma xtal 24mhz, v dd =3.3v 3.2 ma i nternal 22.1184mhz ,v dd =5v 2. 3 ma i nternal 22.1184mhz ,v dd =3.3v 2. 2 ma i idle idle current xtal 12mhz, v dd =5.0v 2.7 ma xtal 24mhz, v dd =5. 5 v 3.7 ma N79E845/844/8432 data s heet april 23 201 4 page 176 of 183 revision a2. 6 table 28 ? 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40~85 c, unless otherwise specified. ) sym parameter test condition s min typ max unit xtal 12mhz, v dd =3.3v 1.3 ma xtal 24mhz, v dd =3.3v 2.3 ma i nternal 22.1184mhz ,v dd =5v 1 . 6 ma i nternal 22.1184mhz ,v dd =3.3v 1. 6 ma i pd power - down mode <5 30 a power - down mode (bod enable) 100 a r rst rst - pin internal pull - h igh resistor 2. 4 v < v dd < 5.5v 100 250 . v bod 38 bod 38 detect voltage ( temp.=25 ) 3. 5 3.8 4 .1 v bod 38 detect voltage ( temp.= 85 ) 3. 5 3.8 4. 9 v bod 38 detect voltage ( temp.= -40 ) 3. 0 3.8 4. 1 v v bod27 bod27 detect voltage ( temp.=25 ) 2. 5 2.7 2.9 v bod27 detect voltage ( temp.= 85 ) 2. 5 2.7 3.1 v bod27 detect voltage ( temp.= -40 ) 2. 4 2.7 2.9 v [1] typical values are not guaranteed. the values listed are tested at room temperature and based on a limited number of samples. [2] pins of ports 0 ,1,3 source a transition current when they are being externally driven from 1 to 0. the transition current rea ches its maximum value when v in is approximately 2v. [3] under steady state (non - transient) conditions, i ol /i oh should be externally limited as follows: N79E845/844/8432 data s heet april 23 201 4 page 177 of 183 revision a2. 6 maximum i ol /i oh of p0,p3 per port pin: 2 0 ma maximum i ol /i oh of p 10, p11, p14, p16, p17 : 38 ma maximum total i ol /i oh for all outputs: 100 ma (through v dd total current) maximum total i ol /i oh for all outputs: 15 0ma (through v ss total current) [4] if i oh exceeds the test condition, v oh will be lower than the listed specification. if i ol exceeds the test condition, v ol will be higher than the listed specification. [5] tested while cpu is kept in reset state. [6] general purpose i/o mean the general purpose i/o, such as p0, p1 , p3 . [7] these parameters are characterized but not tested. other : p1.2 and p1 . 3 are open drain structure . they have not quasi or push pull modes. 28.3 ac electrical characteristics 28.3.1 10- bits sar - adc specification table 28 ? 4 operation voltage symbol min typ max unit operation voltage v dd 2.7 5.5 v resolution 10 bit conversion time 35t adc [1] us sampling rate 150k hz integral non - linearity error inl - 1 1 lsb differential non - linearity dnl - 1 1 lsb gain error ge - 1 1 lsb offset error ofe - 4 4 lsb clock frequency adcclk 5.25 mhz absolute error - 4 4 lsb band - gap v bg 1 1.3 1.6 v [1] t adc the period time of adc input clock N79E845/844/8432 data s heet april 23 201 4 page 178 of 183 revision a2. 6 28.3.2 4 ~ 24 mhz xtal specification s parameter condition min. typ. max. unit input clock frequency external crystal 4 24 mhz parameter symbol min. typ. max. units notes external crystal frequency 1/t clcl 4 24 mhz clock high time t chcx 20.8 - - ns clock low time t clcx 20.8 - - ns clock rise time t clch - - 10 ns clock fall time t chcl - - 10 ns t clcl t clcx t chcx t clch t chcl note: duty cycle is 50%. 28.3.3 internal rc oscillator specification s 22.1184 mhz /11.0592 mhz parameter condition s min. typ. max. unit center frequency 22.1184 /11.0592 mhz internal oscillator frequency +25 0 c at v dd = 5v - 1 +1 % +25 0 c at v dd = 2.7~5.5v - 3 +3 % - 10 0 c~+70 0 c at v dd = 2.7~5.5v - 5 +5 % - 40 0 c~+85 0 c at v dd = 2.7~5.5v - 8 +8 % N79E845/844/8432 data s heet april 23 201 4 page 179 of 183 revision a2. 6 28.3.4 internal rc oscillator specification s 10 khz parameter condition min. typ. max. unit center frequency v dd = 2.4v~5.5v 5 10 15 khz N79E845/844/8432 data s heet april 23 201 4 page 180 of 183 revision a2. 6 29 application circuit for emc i mmunity the application circuit is shown below. the user is recommended follow the circuit enclosed by gray blocks to achieve the most stable and reliable operation of mcu especially in a noisy power environment for a healthy emc immunity. if internal rc oscillato r is used as the clock system , 0 .1f capacitor should be added to gain a precise rc frequency. xtal2 xtal1 v ss /rst vdd gnd v dd 0.1f 0.1f 10f as close to the power source as possible as close to mcu as possible 33 c1 c2 r 100 10f crystal crystal frequency r c1 c2 4mhz~24mhz without d epend on crystal specifications figure 29? 1 application circuit for e ft improvement N79E845/844/8432 data s heet april 23 201 4 page 181 of 183 revision a2. 6 30 package dimensions 30.1 20- pin tssop - 4.4x 6.5 mm N79E845/844/8432 data s heet april 23 201 4 page 182 of 183 revision a2. 6 30.2 16- pin sop - 150 mil N79E845/844/8432 data s heet april 23 201 4 page 183 of 183 revision a2. 6 31 document revision history r e vi sion date description a1.0 - initial preliminary release a2.0 2011/ 10/ 0 5 revise d typos a2. 1 2011/ 1 1/03 re moved the pdip20 package revise d table 12- 3 revise d figure 15- 2 a2.2 2011/ 1 1/23 revised figure 29 - 1 revised chapter 22.1 a2.3 201 2/02/16 revise d the following operation voltage: ?v dd = 2. 4 v to 5.5v at f osc = 4~ 12mhz or internal rc 11.0592mhz? revise d c onfig 3[1:0]=10b as a reserved item revise d operating and idle c urrent s in table 28 ? 2 revise d figure 24 ? 1 a2.4 201 2/05/11 revise d typos revised bod27/38 of t able 28 ? 2 revised p16/p17 of table 5 ? 1 revised figure 6 -1 removed the ? n79e843a? part number revised chapter 21.2 revised chapter 27 a2.5 201 2/0 6/26 revised chapter 2 a2.6 2014 /0 4 / 23 revised 20.2 isp command table revised adc demo code revised sop 16 package removed sop20 package important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfun c- tion or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ? insecure usage ? . insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or s ustain life. all insecure usage shall be made at customer ? s risk, and in the event that third parties lay claims to nuvoton as a result of customer ? s insecure usage, customer shall indemnify the damages and liabil i- ties thus incurred by nuvoton. |
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